Hardware Reference
In-Depth Information
are used to transfer all kinds of information. When communicating with another I
2
C device, the
8 bits of data may be a control code, an address, or data. An example of 8-bit data is shown in
Figure 11.5.
SDA
SCL
Note: Data bit is always stable when clock (SCL) is high
Figure 11.5
■
I
2
C bus data elements
A
CKNOWLEDGE
(ACK) C
ONDITION
Data transfer in the I
2
C protocol needs to be acknowledged either positively (A) or nega-
tively (NACK). As shown in Figure 11.6, a device can acknowledge (A) the transfer of each byte
by bringing the SDA line low during the ninth clock pulse of SCL.
SDA
SDA
SCL
SCL
Figure 11.6
■
ACK condition
Figure 11.7
■
NACK condition
If the device does not pull the SDA line to low and instead allows the SDA line to float high,
it is transmitting a negative acknowledge (NACK). This situation is shown in Figure 11.7.
All masters generate their own clocks on the SCL line to transfer messages on the I
2
C
bus. Data is valid only during the high period of the clock. A defined clock is therefore needed
for the bit-by-bit arbitration procedure to take place. For most microcontrollers (including the
HCS12 devices), the SCL clock is generated by counting down a programmable reload value
using the instruction clock signal.
Clock synchronization is performed using the wired-AND connection of I
2
C interfaces to
the SCL line. This means that a high-to-low transition on the SCL line will cause the devices
concerned to start counting off their low period, and once a device clock has gone low, it will
hold the SCL line in that state until the high state is reached (CLK1 in Figure 11.8). However, the
transition from low to high of this clock may not change the state of the SCL line if another clock
(CLK2) is still within its low period. The SCL line will therefore be held low by the device with
the longest low period. Devices with shorter low periods enter a high
wait state
during this time.
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