The SPI Function - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 524

• Disable mode fault, disable bidirectional mode, stop SPI in wait mode
• Shift data least significant bit first
• Use SS0 pin and enable SS0 output
• Baud rate set to 4 MHz
E10.2 Confi gure the SPI0 module to operate with the following setting:
• Master mode with all interrupt disabled
• SCK0 idle high and data shifted on the rising edge
• Disable mode fault, disable bidirectional mode, SPI0 stops in wait mode
• Data shifted most significant bit first
• Use SS0 pin and enable SS0 output
• Baud rate set to 3 MHz
E10.3 Assume that there is an SPI-compatible peripheral output device that has the following
characteristics:
• A CLK input pin that is used as the data-shifting clock signal. This signal is idle
low and data is shifted in on the rising edge.
• An SI pin to shift in data on the falling edge of the CLK input.
• A CE pin, which enables the chip to shift in data when it is low.
• A highest data-shifting rate of 1 MHz.
• Most significant bit shifted in first.
• All interrupts disabled.
• The SPI0 module stopped in wait mode and freeze mode.
• The SS0 pin used as a general I/O pin.
Describe how to connect the SPI0 pins for the HCS12 and this peripheral device and write an
instruction sequence to confi gure the SPI subsystem properly for data transfer. Assume that the
E-clock frequency is 24 MHz.
E10.4 The 74HC165 is another SPI-compatible shift register. This chip has both serial and
parallel inputs and is often used to expand the number of parallel input ports. The block
diagram of the 74HC165 is shown in Figure E10.4. The operation of this chip is illustrated in
Table E10.4.

V CC D2 D1 DS Q7

CE D3 D0

16 15 14 13 12 11 10 9

74HC165

1 2 3 4 5 6 7 8

PL CP D4 D6 D7

D5 Q7 GND

Figure E10.4 ■ The 74HC165 pin assignment