Hardware Reference
In-Depth Information
The values beginning at GO1 are addresses of potential destinations of the jump instruc-
tions. At the time the jmp [D, PC] instruction is executed, the PC points to the address GO1
and D holds one of the values $0000, $0002, or $0004 (determined by the program some time
before the jmp). Assume that the value in D is $0002. The jmp instruction adds the values in D
and PC to form the address of GO2 and jumps to target2. The locations of target1 through tar-
get3 are known at the time of program assembly, but the destination of the jmp depends on the
value in D computed during program execution.
The HCS12 devices incorporate hardware that supports addressing a larger memory space
than the standard 64 kB. The expanded memory system is accessed by using the bank-switch-
ing scheme. The HCS12 treats the 16 kB of memory space from $8000 to $BFFF as a program
memory window. The HCS12 has an 8-bit program page register (PPAGE), which allows up to
256 16-kB program memory pages to be switched into and out of the program memory window.
This provides up to 4 MB of paged program memory space.
It would be very helpful to learn a small set of HCS12 instructions that are used most often
before we formally learn HCS12 assembly language programming. In the following, we will
examine data movement, addition, and subtraction instructions. The HCS12 provides a large
group of data movement instructions. Some of them may transfer data between a CPU register
and a memory location. Some of them may transfer or exchange data between two registers.
Others may transfer data from one memory location to another memory location.
The load instruction copies the contents of a memory location or places an immediate
value into an accumulator or a register. Memory contents are not changed. Store instruc-
tions copy the contents of a CPU register into a memory location. The contents of the
accumulator or CPU register are not changed. Store instructions automatically update the
N and Z flags in the condition code register (CCR). Table 1.5 is a summary of load and store
instructions.
There are restrictions on the addressing modes that can be used in a load and a store instruction:
•
For the load instruction, all except for the relative addressing mode can be used to select
the memory location or value to be loaded into an accumulator or a CPU register.
•
For the store instruction, all except for the relative and immediate addressing modes
can be used to select the memory location to store the contents of a CPU register.
For example, the following instruction loads the contents of the memory location pointed to by
index register X into accumulator A:
ldaa 0,X
The following instruction loads the contents of the memory location at $1004 into accumulator B:
ldab $1004
The following instruction stores the contents of accumulator A in the memory location at $20:
staa
$20
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