The SPI Function - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 512

D IGIT R EGISTERS
The MAX6952 uses eight digit registers to store the characters that the user wishes to
display on the four 5 7 LED digits. These digit registers are implemented with two planes of

4 bytes, called P0 and P1. Each LED digit is represented by 2 bytes of memory, 1 byte in plane
P0 and the other in plane P1. The digit registers are mapped so that a digit's data can be updated
in plane P0 or plane P1 or both at the same time, as shown in Table 10.10.

×

Segment's
Bit Setting in
Plane P1

Segment's
Bit Setting in
Plane P10

Segment Behavior

0 0 Segment off

0 1 Segment on only during the first

half of each blink period

1 0 Segment on only during the

second half of each blink period

1 1 Segment on

Table 10.10 ■ Digit register mapping with blink globally enabled

If the blink function is disabled through the blink enable bit E in the configuration regis-
ter, then the digit register data in plane P0 is used to multiplex the display. The digit register
data in P1 is not used. If the blink function is enabled, then the digit register data in both plane
P0 and P1 are alternately used to multiplex the display. Blinking is achieved by multiplexing
the LED display using data planes P0 and P1 on alternate phases of the blink clock (shown in
Table 10.10).
The data in the digit registers does not control the digit segments directly. Instead, the
register data is used to address a character generator, which stores the data of a 128-character
font. The lower 7 bits of the digit data (D6 to D0) select the character font. The most significant
bit of the register data (D7) selects whether the font data is used directly (D7 5 0) or whether
the font is inverted (D7 5 1). The inversion feature can be used to enhance the appearance of
bicolor displays by displaying, for example, a red character on a green background.

C ONFIGURATION R EGISTER
The configuration register is used to enter and exit shutdown, select the blink rate, globally
enable and disable the blink function, globally clear the digit data, and reset the blink timing.
The contents of the configuration register are shown in Figure 10.27.

I NTENSITY R EGISTERS
Display brightness is controlled by four pulse-width modulators, one for each display digit.
Each digit is controlled by a nibble of one of the two intensity registers, Intensity10 and Inten-
sity32 . The upper nibble of the Intensity10 register controls the intensity of the matrix display 1,
whereas the lower nibble of the same register controls the intensity of the matrix display 0.
Matrix displays 3 and 2 are controlled by the upper and lower nibbles of the Intensity32 register,
respectively. The modulator scales the average segment current in 16 steps from a maximum
of 15/16 down to 1/16 of the peak current. The minimum interdigit blinking time is, therefore,
1/16 of a cycle. The maximum duty cycle is 15/16.