Hardware Reference
In-Depth Information
7
6
5
4
3
2
1
0
Reset value
= 0x20
SPIF
0 SPTEF
MODF
0
0
0
0
SPIF: SPI interrupt request bit
SPIF is set after the eight SCK cycles in a data transfer, and it is
cleared by reading the SP0SR register (with SPIF set) followed by
a read access to the SPI data register.
0 = transfer not yet complete.
1 = new data copied to SPIxDR.
SPTEF: SPI data register empty interrupt flag
0 = SPI data register not empty.
1 = SPI data register empty.
MODF: mode error interrupt status flag
0 = mode fault has not occurred.
1 = mode fault has occurred.
Figure 10.4
■
SPI status register (SPI
x
SR)
data byte is transmitted immediately after the previous transmission has completed.
Do not
write to the SPIxDR register unless the SPTEF bit is 1
.
Only a master SPI module can initiate transmission. A transmission begins by writing to
the master SPI data register. Data is transmitted and received simultaneously. The serial clock
(SCK) synchronizes shifting and sampling of the information on the two serial data lines. The
SS line allows selection of an individual slave SPI device; slave devices that are not selected do
not interfere with SPI bus activities. Optionally, on a master SPI device, the SS signal can be
used to indicate multiple-master bus contention.
The CPHA and CPOL bits in the SPI
x
CR1 register allow the user to select one of the four
combinations of serial clock phase and polarity. The clock phase control bit (CPHA) selects one
of two fundamentally different transmission formats. Clock phase and polarity should be iden-
tical for the master SPI device and the communicating slave device.
When the CPHA bit is set to 0, the first edge on the SCK line is used to clock the first data bit
of the slave into the master and the first data bit of the master into the slave. In some peripheral
devices, the first bit of the slave's data is available at the slave data out pin as soon as the slave is
selected. In this format, the first SCK edge is not issued until a half-cycle into the 8-cycle trans-
fer operation. The first edge of SCK is delayed a half cycle by clearing the CPHA bit.
The SCK output from the master remains in the inactive state for a half SCK period before
the first edge appears. A half SCK cycle later, the second edge appears on the SCK pin. When this
second edge appears, the value previously latched from the serial data input is shifted into the
least significant bit of the shifter. After this second edge, the next bit of the SPI transfer data is
transmitted out of the MOSI pin of the master to the serial data input pin of the slave device.
This process continues for a total of 16 edges on the SCK pin, with data being latched on odd-
numbered edges and shifted (to the shift register) on even-numbered edges. Data reception is
double-buffered. Data is shifted serially into the SPI shift register during the transfer and is
transferred to the parallel SPI data register after the last bit is shifted in.
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