Hardware Reference
In-Depth Information
7
6
5
4
3
2
1
0
Reset value
= 0x00
0
SPPR2
SPPR1
SPPR0
0
SPR2
SPR1
SPR0
SPPR2 , SPPR0: SPI baud rate preselection bits
SPR2 , SPR0: SPI baud rate selection bits
BaudRateDivisor = (SPPR + 1) × 2 (SPR + 1)
Baud Rate = E-Clock ÷ BaudRateDivisor
Figure 10.3 SPI baud rate register (SPI x BR, x 5 0, 1, or 2)
Example 10.1
Give a value to be loaded into the SPI x BR register to set the baud rate to 2 MHz for a
24-MHz E-clock.
Solution: 24 MHz 4 2 MHz 5 12. By setting SPPR2,SPPR0 and SPR2,SPR0 to 010 and 001,
respectively, we can set the baud rate to 2 MHz. The value to be loaded to the SPI x BR register
is $21.
Example 10.2
What is the highest possible baud rate for the SPI with 24-MHz E-clock?
Solution: The highest SPI baud rate occurs when both SPPR2,SPPR0 and SPR2,SPR0 are set to 000.
Under this condition, the BaudRateDivisor is 2, and hence the baud rate is 24 MHz/2 5 12 MHz.
The SPI has a status register that records the progress of data transfer and errors, as shown
in Figure 10.4. The application program can check bit 7 of the SPI x SR register or wait for the
SPI interrupt to find out if the SPI transfer has completed. When transferring data in higher
frequency using the SPI format, using the polling method is more efficient due to the overhead
involved in interrupt handling.
The setting of the SPIF flag may request an interrupt to the CPU if the SPIE bit of the
SPI x CR1 register is also set to 1.
The SPTEF bit is set when there is room in the transmit data buffer. It is cleared by reading
the SPI x SR register with SPTEF set, followed by writing a data value into the SPI data (SPI x DR)
register. The SPTEF bit is set whenever the byte in the SPI x DR register is transferred to the
transmit shift register. The setting of the SPTEF flag may request an interrupt to the CPU if the
SPTIE bit of the SPI x CR1 register is also set to 1.
The MODF bit is set if the SS input becomes low while the SPI is configured as a master.
The flag is cleared automatically by a read of the SPI x SR register followed by a write to the
SPI x CR1 register. The MODF bit is set only if the MODFEN bit of the SPI x CR2 register is set.
The 8-bit SPI x DR register is both the input and output register for SPI data. A write to this
register allows a byte to be queued and transmitted. For an SPI configured as a master, a queued
 
 
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