Introduction to the HCS12 Microcontroller - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 21

Instruction dbnz 0x21,loop (machine code 5 D5 21 0A)
Step 1
The value in the PC (0x0010) is placed on the program memory address bus with a request
to read the contents of that location.
Step 2
The 8-bit value at the location 0x0010 is the instruction opcode 0xD5. At the end of this
read cycle, the PC is incremented to 0x0011. The program memory returns the opcode
byte 0xD5 to the CPU.
Step 3
The CPU recognizes that it needs to read a data memory address and a branch offset from
the program memory.
Step 4
Processor X performs two more read operations to the program memory. The program
memory returns 0x21 and 0x0A (both are held in IR). At the end of these two read cycles,
the PC is incremented to 0x0013.
Step 5
Processor X places 0x21 on the data memory address bus with a read request. At the end
of the read cycle, the value of the data memory location at 0x21 is returned to the CPU
which will be held in the MDR.
Step 6
Processor X decrements the contents of the MDR. The contents of the MDR are then placed
on the data memory data bus. Processor X also places the address 0x21 on the data memory
address bus with a write request to store the contents of the MDR in data memory.
Step 7
If the value stored in the MDR is not zero, processor X adds 0x0A to the PC and places the
result in the PC (this causes a branch behavior). Otherwise, the PC is not changed.
This section demonstrates the activities that may occur during the execution of a program.
Overall, the operations performed by the processor are dictated by the opcode.
1.7 Overview of the HCS12 Microcontroller
Freescale designed the 68HC12 as an upgrade to the 8-bit 68HC11 microcontroller. However,
Motorola discovered that the performance of the 68HC12 microcontroller was not satisfactory
after it was introduced to the market. The 68HC12 has the highest bus clock speed of 8 MHz. To
be competitive, Freescale revised the design to achieve a bus clock rate of 25 MHz (a few micro-
controllers can run at 33 MHz). The revised 68HC12 was referred to as the Star12 family. It was
also named the HCS12 family. The HCS12 MCU has the same instruction set and addressing
modes as does the 68HC12. However, many of the internal designs have been changed.
Automotive and process control applications are the two major target markets of the
HCS12. This is evidenced by the inclusion of such peripheral functions as input capture (IC),
output compare (OC), pulse-width modulation (PWM), controller area network (CAN), and
byte data link control (BDLC). Other peripheral functions such as serial peripheral interface
(SPI), serial communication interface (SCI), and interintegrated circuit (I 2 C) are also included to
facilitate interconnection with a wide variety of peripheral chips.
Using flash memory to hold application programs has become the trend of microcontroller
design. All HCS12 members incorporate on-chip flash memory to hold programs. Most HCS12