Timer Functions - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 416

subd edge1
std pulse_width
bcc next
; second edge is smaller, so decrement overflow count by 1

ldx overflow

dex

stx overflow

next swi

tov_isr movb #TOF,TFLG2 ; clear the TOF flag

ldx overflow ; increment TCNT overflow count

inx ; “

stx overflow ; “

rti

end

▲
The modification to the C program in Example 8.3 is also minor and hence is left as an
exercise problem.

8.10 Pulse-Width Modulation (PWM) Function

There are many applications that require the generation of digital waveforms. The out-
put-compare function has been used to generate digital waveforms with any duty cycle in Sec-
tion 8.6. However, the generation of waveforms using the output-compare function requires
frequent attention from the MCU. Most microcontrollers designed in the last few years have
incorporated the Pulse-Width Modulation (PWM) function to simplify the task of waveform
generation.
The MC9S12DG256 and many other HCS12 members implement an 8-channel, 8-bit PWM
function. As shown in Figure 8.38, each channel has a period register, a duty cycle register, a
control register, and a dedicated counter to support the waveform generation. The clock signal
is critical to the setting of the frequency of the generated waveform. The clock source of the
counter is programmable through a two-stage circuitry.
The two most important characteristics of a PWM waveform are the period (or frequency)
and the duty cycle of the waveform. The clock source and the period register together deter-
mine the period of the generated waveform whereas the clock select chain sets the frequency
of the clock source to the PWM counter. The period of the PWM waveform is set by placing
an appropriate value into the period register and setting the clock select block properly. The
duty cycle is determined by the ratio of the duty register and the period register.

8.10.1 PWM Clock Select
There are four possible clock sources for the PWM function: clock A, clock B, clock SA
(scaled A), and clock SB (scaled B). These four clocks are derived from the E-clock. Clocks A and
B are derived by dividing the E-clock by a factor of 1, 2, 4, 8, 16, 32, 64, or 128. Clock SA (SB) is
derived by dividing clock A (B) by an 8-bit reloadable counter.
Each PWM channel has the option of selecting one of two clocks, either the prescaled clock
(clock A or B) or the scaled clock (clock SA or SB). Figure 8.39 illustrates the block diagram of
the four different clocks and how the scaled clocks are created.