Timer Functions - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 401

8.7.5 Operations of the Enhanced Pulse Accumulators
The 16-bit PACA has two operation modes: event counting and gated time accumulation.
When in the event-counting mode, the PACA counter increases on the selected edge of the
PT7 signal. The PAIF flag of the PAFLG register is set to 1 whenever the selected signal edge
is detected on the PT7 pin. The setting of this flag may request an interrupt to the MCU if the
PAI bit of the PACTL register is set to 1. When in gated-time-accumulation mode, the 16-bit
counter is enabled to increment by the E/64 clock signal if the selected signal level is applied
on the PT7 pin.
All other pulse accumulators (PACB, PAC3,PAC0) count the number of active edges at
their associated pins. Whenever the PAC3 or PAC1 rolls over from $FF to $00, its associated
flag (PAOVF or PBOVF) will be set to 1 and may optionally request an interrupt to the MCU.
Pulse accumulators PAC2 and PAC0 do not have the interrupt capability. The user can prevent
8-bit pulse accumulators counting further than $FF by setting the PACMX bit in the ICSYS reg-
ister. In this case, a value of $FF means that 255 counts or more have occurred. The contents of
the ICSYS register are illustrated in Figure 8.31.

7 6 5 4 3 2 1 0

Reset value
= 0x00

SH37 SH26 SH15 SH04 TFMOD PACMX BUFEN LATQ

SHxy: share input action of input-capture channel x and y bits
0 = normal operation.
1 = the channel input x causes the same action on the channel y .

TFMOD: timer-flag-setting mode bit
0 = the timer flags C3F:C0F in TFLG1 are set when a valid input-
capture transition on the corresponding port pin occurs.
1 = if in the queue mode (BUFEN = 1 and LATQ = 0), the timer flags
C3F:C0F in TFLG1 are set only when a latch on the corresponding
holding register occurs. If the queue mode is not engaged, the timer
flags C3F:C0F are set the same way as for TFMOD = 0.
PACMX: 8-bit pulse accumulator maximum count bit
0 = normal operation. When the 8-bit pulse accumulator has reached
$FF, with the next active edge, it will be incremented to $00.
1 = when the 8-bit pulse accumulator has reached the value $FF, it
will not be incremented further. The value $FF indicates a count
of 255 or more.
BUFEN: IC buffer enable bit
0 = input-capture and pulse accumulator holding registers are
disabled.
1 = input-capture and pulse accumulator holding registers are
enabled.
LATQ: input-capture latch or queue mode select bit
The BUFEN bit should be set to enable IC and the pulse accumulator's
holding registers. Otherwise, the LATQ latching mode is disabled.
0 = the queue mode of input-capture is enabled.
1 = the latch mode is enabled. Latching function occurs when modulus
down counter reaches 0 or a 0 is written into the count register
MCCNT. With a latching event, the contents of IC registers and
8-bit pulse accumulators are transferred to their holding registers.
The 8-bit pulse accumulators are cleared.

Figure 8.31 ■ Input Control System Control register (ICSYS)