Hardware Reference
In-Depth Information
7
6
5
4
3
2
1
0
Reset value
= 0x00
0
0
0
0
0
0
PAOVF
PAIF
PAOVF: pulse accumulator overflow flag
This flag is set when PACNT overflows from $FFFF to $0000 and can
be cleared by writing a 1 to it.
PAIF: PT7 pin edge flag
When in event-counting mode, this bit is set when the selected edge on the
PT7 pin is detected.
When in gated-accumulation mode, the selected trailing edge sets this
flag.
Figure 8.28
■
Pulse Accumulator Flag register (PAFLG)
7
6
5
4
3
2
1
0
Reset value
= 0x00
0
PBEN
0
0
0
0
PBOVI
0
PBEN: pulse accumulator B system enable bit
0 = 16-bit pulse accumulator disabled. Eight-bit PAC1 and PAC0 can
be enabled when their related enable bits in ICPACR are set.
1 = pulse accumulator B system enabled.
PBOVI: pulse accumulator B overflow interrupt enable bit
0 = interrupt inhibited.
1 = interrupt requested if PBOVF is set.
(a) Pulse accumulator B control register (PBCTL)
7
6
5
4
3
2
1
0
Reset value
= 0x00
0
0
0
0
0
0
PBOVF
0
PBOVF: pulse accumulator B overflow flag
This bit is set when the 16-bit pulse accumulator B overflows from
$FFFF to $0000 or when 8-bit accumulator 1 (PAC1) overflows from
$FF to $00. It is cleared by writing 1 to it or by accessing PACN1 and
PACN0 when the TFFCA bit in the TSCR1 register is set.
(b) Pulse accumulator B flag register (PBFLG)
Figure 8.29
■
Pulse Accumulator B Control and Flag registers
The PACB pulse accumulator is controlled by the PBCTL register, and the PBFLG register
records its status. The contents of these two registers are shown in Figure 8.29.
Each of the 8-bit pulse accumulators can be enabled if its associated 16-bit pulse accumula-
tor is disabled. The enabling of an 8-bit pulse accumulator is done by programming the ICPAR
register. The contents of ICPAR are shown in Figure 8.30.
Each of the 8-bit pulse accumulator also has an 8-bit holding register (PA3H,PA0H).
7
6
5
4
3
2
1
0
Reset value
= 0x00
0
0
0
0
PA3EN
PA2EN
PA1EN
PA0EN
PAxEN: 8-bit pulse accumulator x enable bit
0 = pulse accumulator x disabled
1 = pulse accumulator x enabled
Figure 8.30
■
Input Control Pulse Accumulator Control register (ICPACR)
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