Timer Functions - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 399

Only two (PAC3 and PAC1) of the four 8-bit pulse accumulators may request interrupt to
the MCU. Interrupts are requested whenever PAC3 or PAC1 rolls over from $FF to $00. The
16-bit PACB may request an interrupt to the MCU whenever its upper 8-bit counter (PAC1)
rolls over from $FF to $00.

8.7.4 Registers Related to Pulse Accumulator
The operation of the 16-bit PACA is controlled by the PACTL register. The status of the
PACA is recorded in the PAFLG register. The PACA has a 16-bit counter. Since PACA is formed
by concatenating PAC3 and PAC2, we can use the instruction ldd PAC3 to copy the contents of
the 16-bit counter. To be backward compatible with the 68HC12, the register name PACNT is
added to the header file so that one can also use the instruction ldd PACNT to copy the contents of
the 16-bit counter. The contents of the PACTL and PAFLG registers are shown in Figures 8.27
and 8.28, respectively.

7 6 5 4 3 2 1 0

Reset value
= 0x00

0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI

PAEN: pulse accumulator system enable bit
0 = PACA is disabled (PACN3 and PACN2 can be enabled).
1 = PACA is enabled (PACN3 and PACN2 cannot be enabled).
PAMOD: pulse accumulator mode bit
0 = event counter mode.
1 = gated time accumulation mode.
PEDGE: pulse accumulator edge control bit
For PAMOD = 0 (event counter mode)
0 = falling edges on the PAI pin cause the count to increment.
1 = rising edges on the PAI pin cause the count to increment.
For PAMOD = 1 (gated time acumulation mode)
0 = PAI pin high enables E ÷ 64 clock to pulse accumulator and
the trailing falling edge on the PAI pin sets the PAIF flag.
1 = PAI pin low enables E ÷ 64 clock to pulse accumulator and
the trailing rising edge on the PAI pin sets the PAIF flag.
CLK1 and CLK0: clock select bits
00 = use timer prescaler clock as timer counter clock.
01 = use PACLK as input to timer counter (TCNT) clock.
10 = use PACLK/256 as timer counter clock.
11 = use PACLK/65536 as timer counter clock.
PAOVI: pulse accumulator overflow interrupt enable bit

0 = disable
1 = enable

PAI: PAI pin interrupt enable bit
0 = disabled
1 = enabled

Figure 8.27 ■ Pulse Accumulator Control register (PACTL)

The PACTL register also controls the clock source for the timer counter (TCNT). When the
CLK1 and CLK0 bits are not 00, the PACLK signal (from the PT7 pin) is prescaled by 1, 256, or
65,536 and used as the clock input to the timer counter.
Bits 1 and 0 of the PAFLG register keep track of the status of the operation of the PACA, as
shown in Figure 8.28. Any access to the PAC3 or PAC2 register will clear all the flag bits in the
PAFLG register if the TFFCA bit in the TSCR1 register is set to 1.