Timer Functions - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 396

7 6 5 4 3 2 1 0

FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0

Reset 0 0 0 0 0 0 0 0

Figure 8.24 ■ Contents of the CFORC register

The forced actions are synchronized to the timer counter clock input. The forced output-
compare signal causes pin action but does not affect the timer flag or generate an interrupt.
Normally, the force mechanism would not be used in conjunction with the automatic pin ac-
tion that toggles the corresponding output-compare pin. The contents of CFORC are shown in
Figure 8.24. CFORC always reads as all zeroes.

Example 8.12
▼ Suppose that the contents of the TCTL1 and TCTL2 registers are $D6 and $6E, respec-
tively. The content of the TFLG1 register is $00. What would occur on pins PT7 to PT0 on the
next clock cycle if the value $7F is written into the CFORC register?
Solution: The TCTL1 and TCTL2 registers configure the output-compare actions as shown in
Table 8.2. Since the content of the TFLG1 register is 0, none of the started output-compare op-
erations have succeeded yet.
Because the CFORC register specifies that the output-compare channels 6 to 0 are
to be forced immediately, the actions specified in the fourth column in Table 8.2 occur
immediately.

Register Bit Positions Value Action to Be Triggered

TCTL1 7 6 1 1 Set the PT7 pin to high

5 4 0 1 Toggle the PT6 pin

3 2 0 1 Toggle the PT5 pin

1 0 1 0 Pull the PT4 pin to low

TCTL2 7 6 0 1 Toggle the PT3 pin

5 4 1 0 Pull the PT2 pin to low

3 2 1 1 Set the PT1 pin to high

1 0 1 0 Pull the PT0 pin to low

Table 8.2 ■ Pin actions on PT7-PT0 pins

▲

8.7 Pulse Accumulator

The HCS12 standard timer system has a 16-bit pulse accumulator, PACA, whereas the Enhanced
Captured Timer system has four 8-bit pulse accumulators (PAC3, . . . , PAC0). Two adjacent