Timer Functions - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 395

We use the interrupt-driven approach to implement this algorithm. After starting the first
action on OC7 and OC0, the program will stay in a wait loop to wait for interrupts to be re-
quested from OC7 and OC0. The interrupt service routine will simply start the next output-
compare operation with 15,000 as the delay count. The assembly program that implements this
idea is as follows:
#include “c:\miniide\hcs12.inc”
high_cnt equ 600 ; interval during which pulse is high

delay equ 1500 ; a delay corresponds to the period of 2 kHz

org $1500

lds #$1500

movw #oc7_isr,UserTimerCh7 ; set up OC7 interrupt vector

movw #oc0_isr,UserTimerCh0 ; set up OC0 interrupt vector

movb #$90,TSCR1 ; enable TCNT and fast timer flag clear

movb #$03,TSCR2 ; set prescaler to 8

movb #$81,TIOS ; enable OC7 and OC0

movb #$01,OC7M ; allow OC7 to control OC0 pin

movb #$01,OC7D ; OC7 action on PT0 pin to pull high

movb #$02,TCTL2 ; select pull low as the OC0 action

movb #$81,TIE ; enable OC7 and OC0 to interrupt

ldd TCNT

addd #delay

std TC7 ; start an OC7 operation

addd #high_cnt

std TC0 ; start an OC0 operation

cli ; enable interrupt

loop bra loop ; infinite loop to wait for interrupt

swi

oc7_isr ldd TC7 ; start the next OC7 action with 15,000

addd #delay ; clock cycles delay, also clear the C7F

std TC7 ; flag

rti

oc0_isr ldd TC0 ; start the next OC0 action with 15,000

addd #delay ; clock cycles delay, also clear the C0F

std TC0 ; flag

rti

end

▲

The C language version of this program is very straightforward and hence is left as an exercise.

8.6.6 Forced Output-Compare
There may be applications in which the user requires an output-compare pin action to
occur immediately instead of waiting for a match between TCNT and the proper output-
compare register. This situation arises in the spark-timing control in some automotive engine
control applications. To use the forced output-compare mechanism, the user would write to the
CFORC register with 1s in the bit positions corresponding to the output-compare channels to
be forced. At the next timer count after the write to CFORC, the forced channels will trigger
their programmed pin actions to occur.