Hardware Reference
In-Depth Information
Program memory
address bus
75
20
00
75
21
14
90
20
00
0x0000
CPU
E0
54
03
70
02
05
20
D5
21
0A
Before read
0x75
0x0000
Program memory
data bus
PC
After read
0x0001
PC
Figure 1.5 Instruction 1-opcode read cycle
Data memory
Data memory
address bus
xx
xx
xx
xx
xx
xx
xx
xx
xx
0x20
CPU
xx
xx
xx
Before write
0x0003
xx
xx
xx
xx
0x00
PC
After write
Data memory
data bus
0x0003
xx
PC
Figure 1.6 Instruction 1-data memory write cycle
 
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