Timer Functions - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 367

The timer counter can be stopped (by setting bit 6 of TSCR1) during the wait mode to save more
power. If the timer function is not needed, it can also be stopped during the freeze mode.
All timer interrupt flags can be cleared by writing a 1 to them. However, there is a faster
way to clear timer flags. When bit 4 of the TSCR1 register is set to 1, a read from or a write to
the appropriate TC register will clear the corresponding flag in the TFLG1 register; any access
to the TCNT register will clear the TOF flag, and any access to the PACNT register will clear
the PAOVF and PAIF flags in the PAFLG register. This feature reduces the software overhead in
a separate clear sequence.

8.4.2 Timer System Control Register 2 (TSCR2)
Timer system control register 2 is another register that controls the operation of the timer
counter. Its contents are shown in Figure 8.3. An interrupt will be requested when the TCNT
overflows (when TCNT rolls over from $FFFF to $0000) and bit 7 of TSCR2 is set to 1.
The timer counter needs a clock signal to operate. The clock input to the timer counter
could be the E-clock prescaled by a factor or the PAI pin input prescaled by a factor. The user
has the option to choose the prescale factor. When bit 3 and bit 2 of the PACTL register are 00,
the clock to the TCNT is the E-clock prescaled by a factor. The lowest 3 bits of the TSCR2
register specify the prescale factor for the E-clock, as shown in Table 8.1.

6 5 3 2 1 0

7 4

TOI 0 0 0 TCRE PR2 PR1 PR0

Value
after reset

0 0 0 0 0 0 0 0

TOI: timer overflow interrupt enable bit
0 = interrupt inhibited.
1 = interrupt requested when TOF flag is set.
TCRE: timer counter reset enable bit
0 = counter reset inhibited and counter free runs.
1 = counter reset by a successful output-compare 7.
If TC7 = $0000 and TCRE = 1, TCNT stays at $0000
continuously. If TC7 = $FFFF and TCRE = 1, TOF will never
be set when TCNT rolls over from $FFFF to $0000.

Figure 8.3 ■ Timer System Control register 2

PR2 PR1 PR0 Prescale Factor

0 0 0 1

0 0 1 2

0 1 0 4

0 1 1 8

1 0 0 16

1 0 1 32

1 1 0 64

1 1 1 128

Table 8.1 ■ Timer counter prescale factor