Hardware Reference
In-Depth Information
(or logic for the MCU). The other is between the interface chip (or logic for the MCU) and
the peripheral devices.
The design of parallel ports of today's microcontrollers (including the HCS12) is to allow
the data written into the data register to appear on the output pins directly and allow the
read operation from the data register to obtain the instantaneous voltage levels on the input
port pins.
There is no concern about the synchronization issue. This is quite different from
the era of microprocessors. To perform an I/O operation, the microprocessor needs to make
sure that interface chip for the input device has new data before it reads it or that the inter-
face chip for the output device can handle new data before it sends new data to it. This is
achieved by either polling or interrupt. The interface chip is designed to have status flags to
indicate whether it has new data or can accept new data for output. The interface chip may
use a strobe signal or handshake signals to achieve synchronization between the interface
chip and the peripheral device. This type of synchronization is no longer needed in today's
microcontrollers.
For the serial interface, the data transfer rate between the processor and the interface logic
is much faster than that between the interface logic and the peripheral device. The processor
needs to make sure that there is new data in the interface logic (usually held in a data register)
before reading it. It also needs to make sure that the interface logic can handle more data before
sending new data to the interface logic. This is achieved by using either the polling or the inter-
rupt method to make sure that the new I/O operation can be started.
The synchronization between the interface logic and the peripheral device is achieved by
following certain data transfer protocols. For example, the interface logic and the peripheral
device will use the same clock signal to synchronize data transfer in the synchronous protocol.
The SPI and I
2
C module use this approach. For data transfers that use asynchronous protocols,
both the transmitter and receiver will agree on a common data transfer rate and the receiver
will use a sampling clock signal with a frequency that is a multiple (16, 32, or 64) of the data
rate to detect the incoming data. This is used in the SCI module.
As mentioned in Section 4.10, the user configures an I/O port for input or output by pro-
gramming the associated data direction register. To output, the user writes data to the port data
register. To input, the user reads data from the port data register. Most I/O ports have additional
registers to control their operations, and most I/O pins service multiple purposes. This section
discusses the pins of each parallel I/O port and their registers in more detail.
In expanded mode, both Port A and Port B are used as time-multiplexed address or data
pins. When configured in single-chip mode, these two ports are used as general-purpose I/O
ports. Each Port A or Port B pin can be configured as an input or output pin. When the HCS12 is
configured in expanded mode, Port A carries the time-multiplexed upper address and data sig-
nals (A15/D15,A8/D8), whereas Port B carries the time-multiplexed lower address and data
signals (A7/D7,A0/D0).
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