Interrupts, Clock Generation, Resets, and Operation Modes - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 298

Reset is a mechanism for
1. Setting up operation mode for the microcontroller
2. Setting up initial values for control registers
3. Exiting from software errors and some hardware errors
All HCS12 microcontrollers have the same number of resets and nonmaskable interrupt
sources despite the fact that they may not have the same number of maskable interrupts. The
HCS12 has two low-power modes that are triggered by the execution of wai and stop instructions.
Power consumption will be reduced dramatically in either low-power mode. The HCS12 has a
COP timer reset mechanism to detect the software error. A software program that behaves prop-
erly will reset the COP timer before it times out and prevent it from resetting the CPU.
The HCS12 has a clock monitor reset mechanism that can detect the slowing down or loss
of clock signals. Whenever the clock frequency gets too low, the clock monitor will detect it
and reset the CPU.
The real-time interrupt (RTI) mechanism, when enabled, generates periodic interrupts to
remind the CPU to perform routine work such as time-multiplexing seven-segment displays,
environment monitoring, task switching in a multitasking operating system, and so on.
The HCS12 has seven different operation modes divided into two basic categories: normal
modes and special modes. Normal modes are used for embedded applications, whereas special
modes are used in fabrication testing and development debugging activities.

6.13 Exercises

E6.1 What is the name given to a routine that is executed in response to an interrupt?
E6.2 What are the advantages of using interrupts to handle data inputs and outputs?
E6.3 What are the requirements for interrupt processing?
E6.4 How do you enable other interrupts when the HCS12 is executing an interrupt service
routine?
E6.5 Why would there be a need to promote one of the maskable interrupts to the highest prior-
ity among all maskable interrupts?
E6.6 Write the assembler directives to initialize the IRQ interrupt vector located at $3000 for
the EVB mode of the D-Bug12 monitor.
E6.7 What is the last instruction in most interrupt service routines? What does this in-
struction do?
E6.8 Suppose that the HCS12 is executing the following instruction segment and the IRQ
interrupt occurs when the TSY instruction is being executed. What will be the contents of the
top 10 bytes in the stack?
org $2000

lds #$2000

clra
ldx #$0

bset 10,X $48

ldab #$40

inca
tap
pshb
tsy
adda #10