Hardware Reference
In-Depth Information
The background debug mode (BDM) is a system development and debug feature and is available
in all modes. In special single-chip mode, BDM is active immediately after reset.
These modes provide three operation configurations. Background debugging is available in
all three modes, but must first be enabled for some operations by means of a BDM command.
BDM can then be made active by another command.
N
ORMAL
E
XPANDED
W
IDE
M
ODE
In this mode, Ports A and B are used as the multiplexed 16-bit address and data buses.
ADDR[15..8] and DATA[15..8] are multiplexed on Port A. ADDR[7..0] and DATA[7..0] are mul-
tiplexed on Port B.
N
ORMAL
E
XPANDED
N
ARROW
M
ODE
The 16-bit external address bus uses Port A for the high byte and Port B for the low byte. The
8-bit external data bus uses Port A. ADDR[15..8] and DATA[7..0] are multiplexed on Port A.
N
ORMAL
S
INGLE
-C
HIP
M
ODE
Normal single-chip mode has no external buses. Ports A, B, and E are configured for gen-
eral-purpose I/O. Port E bits 1 and 0 are input only with internal pull-ups and the other 22 pins
are bidirectional I/O pins that are initially configured as high-impedance inputs. Port E pull-ups
are enabled on reset. Port A and B pull-ups are disabled on reset.
Special operation modes are commonly used in factory testing and system development.
S
PECIAL
E
XPANDED
W
IDE
M
ODE
This mode is for emulation of normal expanded wide mode and emulation of normal
single-chip mode with a 16-bit bus. The bus-control pins of Port E are all configured for their
bus-control output functions rather than general-purpose I/O.
S
PECIAL
E
XPANDED
N
ARROW
M
ODE
This mode is for emulation of normal expanded narrow mode. External 16-bit data is han-
dled as two back-to-back bus cycles, one for the high byte followed by one for the low byte.
Internal operations continue to use full 16-bit data paths.
S
PECIAL
S
INGLE
-C
HIP
M
ODE
This mode can be used to force the microcontroller to active BDM to allow a system debug
through the BKGD pin. The HCS12 CPU does not fetch the reset vector or execute application
code as it would in other modes. Instead, the active background mode is in control of CPU
execution, and BDM firmware waits for additional serial commands through the BKGD pin.
There are no external address and data buses in this mode. The microcontroller operates as a
stand-alone device, and all program and data space are on-chip. External port pins can be used
for general-purpose I/O.
S
PECIAL
P
ERIPHERAL
M
ODE
The HCS12 CPU is not active in this mode. An external master can control on-chip pe-
ripherals for testing purposes. It is not possible to change to or from this mode without going
through reset. Background debugging should not be used while the microcontroller is in special
peripheral mode, as internal bus conflicts between the BDM and the external master can cause
improper operation of both modes.
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