Interrupts, Clock Generation, Resets, and Operation Modes - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 295

V DD

V DD

4.7 k Ω

2μ F

IN

Manual reset

1

RESET

MC34064

4.7 k Ω

GND
3

4.7 k Ω

To RESET
of HCS12

Figure 6.18 ■ A typical external reset circuit

6.11 HCS12 Operation Modes

As shown in Table 6.5, the HCS12 can operate in eight different modes. Each mode has
a different default memory map and external bus configuration. After reset, most system re-
sources can be mapped to other addresses by writing to the appropriate control registers.
The states of the BKGD, MODB, and MODA pins when the RESET signal is low determine
the operation mode after the CPU leaves the reset state. The SMODN, MODB, and MODA bits
in the MODE register show the current operation mode and provide limited mode switching
during the operation. The states of the BKGD, MODB, and MODA pins are latched into these
bits on the rising edge of the RESET signal. During reset, an active pull-up (on-chip transistor) is
connected to the BKGD pin (as input) and active pull-downs (on-chip transistors) are connected
to the MODB and MODA pins. If an open circuit occurs on any of these pins, the device will
operate in normal single-chip mode.
The two basic types of operation modes are
1. Normal modes. Some registers and bits are protected against accidental changes.
2. Special modes. Greater access for special purposes such as testing and emulation to
protected control registers and bits is allowed.

BKGD MODB MODA Mode Port A Port B

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Special single chip
Special expanded narrow
Special peripheral
Special expanded wide
Normal single chip
Normal expanded narrow
Reserved (forced to peripheral)
Normal expanded wide

General-purpose I/O
ADDR[15:8]DATA[7:0]
ADDR/DATA
ADDR/DATA
General-purpose I/O
ADDR[15:8]DATA[7:0]
2
ADDR/DATA

General-purpose I/O
ADDR[7:0]
ADDR/DATA
ADDR/DATA
General-purpose I/O
ADDR[7:0]
2
ADDR/DATA

Table 6.5 ■ HCS12 mode selection