Interrupts, Clock Generation, Resets, and Operation Modes - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 272

RAM Vector
Address

RAM Vector
Address

Interrupt Source Interrupt Source

Reserved $FF80
Reserved $FF82
Reserved $FF84
Reserved $FF86
Reserved $FF88
Reserved $FF8A
PWM emergency shutdown
Port P interrupt
MSCAN 4 transmit
MSCAN 4 receive
MSCAN 4 errors
MSCAN 4 wake-up
MSCAN 3 transmit
MSCAN 3 receive
MSCAN 3 errors
MSCAN 3 wake-up
MSCAN 2 transmit
MSCAN 2 receive
MSCAN 2 errors
MSCAN 2 wake-up
MSCAN 1 transmit
MSCAN 1 receive
MSCAN 1 errors
MSCAN 1 wake-up
MSCAN 0 transmit
MSCAN 0 receive
MSCAN 0 errors
MSCAN 0 wake-up
Flash
EEPROM
SPI2
SPI1

$3E00
$3E02
$3E04
$3E06
$3E08
$3E0A
$3E0C
$3E0E
$3E10
$3E12
$3E14
$3E16
$3E18
$3E1A
$3E1C
$3E1E
$3E20
$3E22
$3E24
$3E26
$3E28
$3E2A
$3E2C
$3E2E
$3E30
$3E32
$3E34
$3E36
$3E38
$3E3A
$3E3C
$3E3E

IIC bus
BDLC
SCME
CRG clock
Pulse accumulator B overflow
Modulus down counter underflow
Port H interrupt
Port J interrupt
ATD1
ATD0
SCI1
SCI0
SPI0
Pulse accumulator A input edge
Pulse accumulator A overflow
Timer overflow
Timer channel 7
Timer channel 6
Timer channel 5
Timer channel 4
Timer channel 3
Timer channel 2
Timer channel 1
Timer channel 0
Real-time interrupt
IRQ
XIRQ
swi
Unimplemented instruction trap
N/A
N/A
N/A

$3E40
$3E42
$3E44
$3E46
$3E48
$3E4A
$3E4C
$3E4E
$3E50
$3E52
$3E54
$3E56
$3E58
$3E5A
$3E5C
$3E5E
$3E60
$3E62
$3E64
$3E66
$3E68
$3E6A
$3E6C
$3E6E
$3E70
$3E72
$3E74
$3E76
$3E78
$3E7A
$3E7C
$3E7E

Table 6.2 ■ D-Bug12 RAM interrupt vector address

If an unmasked interrupt occurs and a table entry contains the default address of $0000, pro-
gram execution is returned to D-Bug12. The D-Bug12 would display a message indicating the
source of the interrupt and also display the CPU registers at the point where the program was
interrupted. The only exception to this is the SCI0 interrupt. Even though there is an entry for
SCI0 in Table 6.2, one cannot use the SCI0 interrupt because it has been used by D-Bug12 for all
of its communications. The hcs12.inc (and hcs12.h ) file also provides the mnemonic name for each
interrupt source so that the user can use the mnemonic name to specify the SRAM vector address.
The complete list of these mnemonic names is shown in Table 6.3.