Hardware Reference
In-Depth Information
When a nonmaskable interrupt is recognized, both the X and I bits are set after CPU
registers are saved. The X bit is not affected by maskable interrupts. The execution of an RTI
instruction at the end of the XIRQ service routine will restore the X and I bits to the preinter-
rupt request state.
U
NIMPLEMENTED
O
PCODE
T
RAP
The HCS12 uses up to 16 bits (2 pages) to encode the opcode. All 256 combinations in the
page 1 opcode map have been used. However, only 54 of the 256 positions on page 2 of the op-
code map are used. If HCS12 attempts to execute one of the 202 unused opcodes on page 2, an
unimplemented opcode trap occurs. The 202 unimplemented opcodes are essentially interrupts
that share a common interrupt-vector address, $FFF8:$FFF9. The HCS12 uses the next address
after an unimplemented page 2 opcode as a return address.
S
OFTWARE
I
NTERRUPT
I
NSTRUCTION
(
SWI
)
Execution of the swi instruction causes an interrupt without an interrupt request signal.
swi is not inhibited by the global mask bits in the CCR. So far, we have been using this instruc-
tion to jump back to the D-Bug12 monitor.
The swi instruction is commonly used in the debug monitor to implement
breakpoints
and
to transfer control from a user program to the debug monitor. A breakpoint in a user program is a
memory location where we want program execution to be stopped and information about instruc-
tion execution (in the form of register contents) to be displayed. To implement breakpoints, the
debug monitor sets up a breakpoint table. Each entry of the table holds the address of the breakpoint
and the opcode byte at the breakpoint. The monitor also replaces the opcode byte at the break-
point with the opcode of the swi instruction. When the instruction at the breakpoint is executed, it
causes an swi interrupt. The service routine of the swi interrupt will look up the breakpoint table
and take different actions depending on whether the saved PC value is in the breakpoint table:
Case 1
The saved PC value is not in the breakpoint table. In this case, the service routine will
simply replace the saved PC value (in the stack) with the address of the monitor program
and return from the interrupt.
Case 2
The saved PC is in the breakpoint table. In this case, the service routine will
1. Replace the swi opcode with the opcode in the breakpoint table
2. Display the contents of the CPU registers
3. Replace the saved PC value (in the stack) with the address of the monitor program
4. Return from the interrupt (return to the debug monitor because of step 3)
Most users would use the EVB mode of the D-Bug12 monitor to develop applications on a
demo board having the D-Bug12 monitor. However, the D-bug12 monitor's EVB mode does not
allow the use of the on-chip flash memory, which prevents using the default interrupt-vector
table to hold interrupt vectors. To allow the user to develop interrupt-driven applications, the
D-Bug12 monitor provides an SRAM-based interrupt-vector table. This table starts at $3E00 and
has 64 entries of 2 bytes each. The contents of this table are shown in Table 6.2. Initially, all
entries in the table contain an address of $0000. Storing a value other than $0000 in any of the
RAM interrupt-vector table entries causes execution of the interrupt service routine pointed to
by the address when an associated interrupt occurs.
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