Interrupts, Clock Generation, Resets, and Operation Modes - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 264

ignore a maskable interrupt by setting or clearing an enable bit . When an interrupt is enabled,
the CPU will respond to it. When an interrupt is disabled, the CPU will ignore it. An interrupt is
said to be pending when it is active but not yet serviced by the CPU. A pending interrupt may or
may not be serviced by the CPU, depending on whether or not it is enabled.
To make the interrupt system more flexible, a computer system normally provides a global
and local interrupt masking capability. When none of the interrupts are desirable, the processor
can disable all the interrupts by clearing the global interrupt enable bit (or setting the global inter-
rupt mask bit for some other processor). In other situations, the processor can selectively enable
certain interrupts while at the same time disabling other undesirable interrupts. This is achieved
by providing each interrupt source an enable bit in addition to the global interrupt mask. When-
ever any interrupt is undesirable, it can be disabled while at the same time allowing other inter-
rupt sources to be serviced (attended) by the processor. Today, almost all commercial processors
are designed to provide this two-level (or even three-level) interrupt-enabling capability.
6.2.4 Interrupt Priority
If a computer is supporting multiple interrupt sources, then it is possible that several in-
terrupts would be pending at the same time. The CPU has to decide which interrupt should
receive service first in this situation. The solution is to prioritize all interrupt sources. An in-
terrupt with higher priority always receives service before interrupts at lower priorities. Many
microcontrollers, including the HCS12, prioritize interrupts in hardware. For those microcon-
trollers that do not prioritize interrupts in hardware, the software can be written to handle
certain interrupts before others. By doing this, interrupts are essentially prioritized. For most
microprocessors and microcontrollers, interrupt priorities are not programmable.
6.2.5 Interrupt Service
The CPU provides service to an interrupt by executing a program called an interrupt service
routine. After providing service to an interrupt, the CPU must resume normal program execu-
tion. How can the CPU stop the execution of a program and resume it later? It achieves this
by saving the program counter and the CPU status information before executing the interrupt
service routine and then restoring the saved program counter and CPU status before exiting the
interrupt service routine. The complete interrupt service cycle involves
1. Saving the program counter value
2. Saving the CPU status (including the CPU status register and some other registers) in
the stack (This step is optional for some microcontrollers and microprocessors.)
3. Identifying the source of the interrupt
4. Resolving the starting address of the corresponding interrupt service routine
5. Executing the interrupt service routine
6. Restoring the CPU status from the stack
7. Restoring the program counter from the stack
8. Resuming the interrupted program
For all maskable hardware interrupts, the microprocessor starts to provide service when it
completes the execution of the current instruction (the instruction being executed when the
interrupt occurred). For some nonmaskable interrupts, the CPU may start the service without
completing the current instruction. Many software interrupts are caused by an error in instruc-
tion execution that prevents the instruction from being completed. The service to this type of
interrupt is simply to output an error message and abort the program.