Hardware and Software Development Tools for the HCS12 - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 139

uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to
indicate the start of each bit time. This falling edge is sent for every bit whether data is transmit-
ted or received. Data is transferred most significant bit first at 16 target clock cycles per bit. The
interface times out if 512 clock cycles occur between falling edges from the development host.
The BDM module implements a set of hardware and software commands that allows the
external debug adapter to access CPU registers and memory locations to facilitate software debug
activities. For hardware Read commands, the development host must wait for 150 clock cycles after
sending the address before attempting to obtain the read data. For hardware Write commands, the
host must wait for 150 clock cycles after sending data to be written before attempting to send a new
command. For firmware Read commands, the external host should wait for 44 clock cycles before
attempting to obtain the read data. For firmware Write commands, the external host must wait for
32 clock cycles after sending data to be written before attempting to send a new command.
The detailed timing of the BDM serial interface and the BDM commands are beyond the
scope of this text. Interested readers should refer to the Background Debug Module Guide pub-
lished by Freescale.

3.10 The BDM-Based Debugger

The block diagram of a BDM-based development system is shown in Figure 3.42. The BDM pod
is connected to the target board via a BDM cable. To promote the portability of tools that use BDM
mode, Freescale defines a 6-pin connector to be installed on the target board, shown in Figure 3.43.

Host PC

Target Board

Cable BDM cable

BDM pod

6-pin BDM connector

Figure 3.42 ■ BDM development system

BKGD 1 2 GND

NC 3 4 RESET

V FP 5 6 V DD

Figure 3.43 ■ BDM tool connector