Hardware and Software Development Tools for the HCS12 - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 128

Figure 3.26 ■ Select absolute or a relocatable assembly

• The need to set up system clock. The HCS12 includes an on-chip phase-locked-
loop (PLL) circuit that allows the user to use a low-frequency crystal oscillator
(e.g., 4 MHz or 8 MHz) to generate a higher-frequency E-clock signal. To achieve
this, the user will need to write and call a subroutine similar to the following to
multiply the frequency (this has been done in the D-Bug12 monitor):
; ********************************************************************************
; The following subroutine enables PLL and uses an external oscillator to generate the system
; clock. Set the system clock (E-clock) to 24 MHz from a 4-MHz external crystal oscillator.
; ********************************************************************************
SetClk movb #0,REFDV ; set SYSCLK to 24 MHz from a 4 MHz oscillator

movb #$05,SYNR ; “

; movb #$02,SYNR ; use this value if external oscillator is 8 MHz

movb #$60,PLLCTL ; turn on PLL, select high-bandwidth filter

brclr CRGFLG,LOCK,* ; wait until PLL lock into target frequency

bset CLKSEL,PLLSEL ; use PLL to derive system clock

rts
The functioning and programming of the HCS12 on-chip phase-locked-loop are discussed
in Chapter 6. To call this subroutine to set up the system clock, add the following instruction
to your program:
jsr SetClk