Hardware Reference
In-Depth Information
tests bit six and bit two of accumulator A and updates the Z and N fl ags of the CCR register ac-
cordingly. The V fl ag in CCR register is cleared. The instruction
bitb #$22
tests bit fi ve and bit one of accumulator B and updates the Z and N fl ags of CCR register accord-
ingly. The V fl ag in the CCR register is cleared. The instruction
bset 0,y,$33
sets bits fi ve, four, one, and zero of the memory location pointed to by index register Y.
The HCS12 uses the bus clock (we will call it the E-clock from now on) signal as a timing
reference. The generation of the E-clock is described in Chapter 6. The execution times of in-
structions are also measured in E cycles. The execution time of each instruction can be found
in the column “Access Detail” in Appendix A. The number of letters in that column indicates
the number of E cycles that a specific instruction takes to complete the execution. For example,
the Access Detail column of the
pula
instruction contains three letters, ufo, which indicates
that the pula instruction takes three E cycles to complete.
There are many applications that require the generation of time delays. Program loops are
often used to create a certain amount of delay unless the time delay needs to be very accurate.
The creation of a time delay involves two steps.
1. Select a sequence of instructions that takes a certain amount of time to execute.
2. Repeat the instruction sequence for the appropriate number of times.
For example, the following instruction sequence takes 40 E-clock cycles to execute:
loop
psha
; 2 E cycles
pula
; 3 E cycles
psha
pula
psha
pula
psha
pula
psha
pula
psha
pula
psha
pula
nop
; 1 E cycle
nop
; 1 E cycle
dbne
x,loop
; 3 E cycles
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