Cryptography Reference
In-Depth Information
WSN devices have to meet requirements that are usually specific to a given appli-
cation, but we can still distinguish several common features. Nodes should be small,
cheap, energy efficient, equipped with the right set of sensors, and have enough mem-
ory and computational power to perform given tasks. Wireless communication within
the network should be highly reliable even in the face of interference and link fail-
ures. The WSN design space is very large, and hardware platforms are supposed to
support more than one type of application. Due to the large variety in mote design
and parameters (memory size, microcontroller type, and speed), it is hard to develop a
universal security solution that would fit all hardware architectures. For cryptography
implementations, available memory and specific CPU features are the most important
parameters. The security solutions that target WSNs should be optimized and work
with the most constrained devices (typically low-end 8-bit platforms).
From many available architectures, we can choose several devices that are the most
popular platforms at the moment. Each of these motes might be regarded as a repre-
sentative of a certain class of sensor devices. The MICA2DOT represents nodes with
the most limited resources available. It is one of the smallest commercially available
motes and is powered by a 3V coin cell. MICAz is a widely recognized 8-bit sensor
platform used in many different WSN research projects. Tmote Sky is a slightly more
powerful device, with 16-bit processing and a broad range of sensors embedded on the
main Printed Circuit Board (PCB). In addition, Imote2 represents the most power-
ful group of 32-bit sensor platforms that have a lot more capabilities than previously
mentioned nodes.
Cryptographic primitives are based on arithmetic operations, and their efficiency
depends mainly on the hardware support of a given microprocessor. In cryptography,
we have to deal with large numbers that can have more than 1000 bits. Arithmetic on
such large integers is a time-consuming task, especially on 8-bit CPUs. To optimize
those operations, we need to take advantage of all the specific features of a given device.
Typical devices have 8- or 16-bit architectures and clock speeds around 4-8 MHz.
The data memory available can be as low as 4 KB, and program storage might be
limited to only 48 KB. These constraints make it difficult to implement some of the
more complex security primitives (as required in PKC).
9.5.1 MICAz/MICA2 Mote
The MICAz mote sensor node is equipped with an ATmega128 8-bit processor clocked
at 7.3728 MHz. The program code is loaded from an 128-KB EEPROM chip, and
runtime memory is stored in a 4-KB RAM chip. The ATmega128 processor is a typical
RISC architecture with 32 registers, but six of them are special pointer registers. Since
at least one register is needed to store temporary results or data loaded from memory,
25 registers are generally available for arithmetic. The instruction set is also reduced,
as only 1-bit shift/rotate instructions are natively supported. Bitwise shifts by arbitrary
amounts can then be implemented with combinations of shift/rotate instructions and
other instructions. The processor pipeline has two stages, and memory instructions
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