Hardware Reference
In-Depth Information
τ
1
τ
2
τ
3
τ
4
0
1
2
3
4
5
6
7
8
9
10
11
12
R
4
11
10
9
8
7
6
5
4
3
2
1
0
t
0
1
2
3
4
5
6
7
8
9
10
11
12
Figure 4.16
Example of schedule produced by DM and response time experienced by
τ
4
as a function of the considered interval.
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