Hardware Reference
In-Depth Information
orders of magnitude higher in terms of IOPS and one order of magnitude
higher in terms of throughput. At this regime, bottlenecks shift from the
devices to the host I/O path and reveal many of the shortcomings of today's
I/O path design in the operating system kernel.
Modern systems introduce significant complexity due to the non-uniform
memory architectures they employ. The I/O path and all the buffers and
structures it uses are shared across all contexts that perform I/O. Therefore,
access to memory results in poor locality. NUMA effects result in both high
overheads and poor scalability as well.
Multicore systems present additional opportunities for improved I/O per-
formance by trading CPU for memory eciency. The dynamic random access
memory (DRAM) I/O cache is most important for reducing the number of
I/O operations, e.g., by absorbing metadata I/O operations and allowing de-
vices to serve mostly data I/O operations. More ecient use of the I/O cache
can significantly improve I/O performance.
In addition, modern servers and applications typically use a large number
of contexts, e.g., threads, that issue I/O requests. However, large numbers of
outstanding requests typically result in mixed patterns that degrade device
performance. Jung et al. [7], explain that even with modern SSDs, small and
non-sequential I/Os result in significantly lower than nominal device perfor-
mance. Therefore, the scheduler will play an increasingly important role, as
workloads become more diverse.
32.3 Storage I/O in the Near Future
Current technology trends stipulate that the number of cores will be in-
creasing and that the persistent I/O hierarchy will include additional types of
non-volatile devices besides SSDs and HDDs. In this landscape, all issues dis-
cussed will intensify and multiple aspects of today's I/O path in the operating
system kernel will need to be redesigned to satisfy future I/O requirements as
Shoaib Akram et al. show [1]. At a high level, some solutions will be introduced
for the following:
Dealing with NUMA servers
Improving the eciency of DRAM caching
Dealing with mixed I/O patterns
Generally, the I/O path is designed as a shared resource. This approach,
although it is flexible and provides a convenient single-system image, it does
not scale as the number of cores and the required levels of I/O performance
increase. Therefore, in the future, the I/O path is expected to be redesigned
