Hardware Reference
In-Depth Information
Chapter 18
GLEAN
Venkatram Vishwanath, Huy Bui, Mark Hereld, and Michael E.
Papka
Argonne National Laboratory
18.1
Motivation :::::::::::::::::::::::::::::::::::::::::::::::::::::::: 215
18.2
Design and Architecture ::::::::::::::::::::::::::::::::::::::::: 216
18.2.1
Exploiting Network Topology and Reduced
Synchronization for I/O ::::::::::::::::::::::::::::::::: 217
18.2.2
Leveraging Application Data Semantics :::::::::::::::: 218
18.2.3
Asynchronous Data Staging ::::::::::::::::::::::::::::: 219
18.2.4
Compression and Subling ::::::::::::::::::::::::::::: 219
18.3
Deployment, Usage, and Applications ::::::::::::::::::::::::::: 220
18.3.1
Checkpoint, Restart, and Analysis I/O for HACC
Cosmology ::::::::::::::::::::::::::::::::::::::::::::::: 220
18.3.2
Data Staging for FLASH Astrophysics :::::::::::::::::: 221
18.3.3
Co-Visualization for PHASTA CFD Simulation :::::::: 222
18.4
Conclusion :::::::::::::::::::::::::::::::::::::::::::::::::::::::: 223
Bibliography :::::::::::::::::::::::::::::::::::::::::::::::::::::: 223
18.1 Motivation
While the computational power of supercomputers continues to increase
with every generation, the I/O systems have not kept pace, resulting in a sig-
nificant performance bottleneck. Further impeding progress, one often finds
that existing I/O solutions only achieve a fraction of quoted capabilities.
On the Argonne Leadership Computing Facility's (ALCF) Blue Gene/P re-
source, FLASH, an astrophysics simulation with a highly tuned I/O subsys-
tem, achieves only 10% of the potential throughput. As the HPC community
pushes toward larger-scale systems and the anticipated increase in the size
of datasets, this situation will only become even more critical. I/O infras-
tructures at extreme scales face several system challenges. At the node level,
one expects a deep and complex memory hierarchy, including non-volatile
memory, as well as higher levels of concurrency. At the system level, leader-
ship computing systems are being architected with higher radix interconnect
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