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impact on the monitored application, they often have a significant implementation over-
head that limits their scalability. In this paper, we propose to utilize the computing
power that is available on-chip emerging heterogeneous multicore processors to detect
data races.
Integration of data-parallel accelerator cores with CPU cores on the same chip has
emerged as a new trend to facilitate energy-efficient computing with diverse cores. The
AMD Fusion APU [7], Intel Sandy Bridge [8], and Nvidia Project Denver [9] are be-
coming part of mainstream computing. The data-parallel cores in these designs can
support a significant number of parallel threads providing computing power needed for
executing data race detection algorithms efficiently. When these cores are not being em-
ployed for performance acceleration, we propose to utilize them for detecting data races
in the application executing on the CPU cores. Without loss of generality, we consider
the Graphics Processing Unit (GPU) as the data-parallel accelerator in our proposal.
In the following sections, we refer to our design as GUARD which stands for GPU
Accelerated Data Race Detector.
The volume of the memory access trace information generated makes it difficult for
a data race detection mechanism to process the trace at runtime. GUARD handles this
by encapsulating the trace generated by the CPU cores into signature. Compacting the
memory access trace also helps in reducing the communication cost between the CPU
and GPU cores. GUARD is also able to provide trade-offs among the two main char-
acteristics of a data race detector:
performance
and
accuracy
. GUARD improves the
performance of the data race detection algorithm by parallelizing the GPU kernel at
different levels. By doing so, GUARD is able to perform data race detection at near-
zero performance overhead. Additionally, to improve the accuracy of data race detec-
tion in the presence of signatures, we introduce a novel filtering mechanism that uses
coherence state information in the cache line to filter out innocuous accesses. Overall,
GUARD proves to be a highly customizable tool which can trade-off between speed
and accuracy to achieve a particular performance-vs-precision goal.
2
Background and Related Work
When two threads access the same memory location without a separating synchroniza-
tion, and at least one of the accesses is a write, there is a data race. A data race could
lead to incorrect or unexpected program behavior, and is a potential security risk. An
example of a data race is shown in Figure 1, where
thread0
and
thread1
access the same
memory location
addr2
. This is a potential concurrency bug as thread0 could modify
the value at address addr2 before its next intended use by thread1. Data races can be
divided into three categories: (i) read-after-write (RAW); (ii) write-after-read (WAR);
and (iii) write-after-write (WAW). A WAR data race condition is shown in Figure 1. Not
all data races are hazardous or potential security risks; some of them could be benign.
However, it is essential for data race detectors to identify and evaluate all potential data
race conditions. Due to space limitations, we only discuss selected work that are closely
related to GUARD in this section.
