Digital Signal Processing Reference
In-Depth Information
and have analyzed their effects on the system performance [9]. To further
decrease the computation cost for low-resource implementations, partial
update NLMS algorithms have been employed in combination with the
convergence improvement techniques [10].
To improve the performance of SAF systems in diffuse noise fields, a
hybrid system was proposed that takes advantage of the complementary
characteristics of subband adaptive and Wiener filtering, resulting in a much
higher noise reduction performance for diffuse noise fields [4]. Here we
briefly introduce the employed OS-SAF system.
Shown in Figure 10-1 is the block diagram of the employed enhancement
system. Two identical analysis filterbanks split the two inputs: the reference
(noise) signal
x(n)
and the primary (noisy) signal
y(n)
into subband signals.
After decimation by a factor of
R
, two subband signal sets
and are obtained. Next,
a subband processing block (denoted by SPB in Figure 10-1, described
below) reduces the noise in each frequency subband. Finally, the synthesis
filterbank combines the subband enhanced signals
to obtain a time-domain output
z
(
n
) .
2.2
The DSP System
We employ highly oversampled GDFT uniform analysis/synthesis
filterbanks based on Weighted OverLap-Add (WOLA). The WOLA
filterbanks are optimally implemented on an ultra-low power hardware
platform depicted in Figure 10-2.
The DSP portion consists of three major components: a WOLA filterbank
coprocessor, a 16-bit DSP core, and an input-output processor (IOP). The
DSP core, WOLA coprocessor, and IOP run in parallel and communicate
through shared memory. The parallel operation of the system enables the
implementation of complex signal processing algorithms in low-resource
environments with low system clock rates. The system is especially efficient
for stereo subband processing.
The core has access to two 4-kword data memory spaces, and another 12-
kword memory space used for both program and data. The core provides 1
MIPS/MHz operation and has a maximum clock rate of 4 MHz at 1 volt. At
1.8 volts, 33 MHz operation is also possible. The system operates on 1 volt
(i.e., from a single battery). The input-output processor is responsible for
management of incoming and outgoing samples. It takes as input the speech
signal sampled by the 16-bit A/D converter on the analog portion of the chip
at a frequency of 8 kHz. The analog portion of the chip also applies a DC-
