UWB for Around-the-Body Data Streaming - Ultra-Wideband and 60 GHz Communications for Biomedical Applications - page 62

RX Digital Baseband
A digital receiver baseband, currently mapped on a Xilinx Virtex 5 FPGA, processes
the 5 bits quantized I and Q baseband signals and controls the receiver frontend.
The digital baseband contains an ASIP core in combination with ASIC acceleration
blocks. The implemented design is divided into multiple clock domains to reduce
the power consumption. The compute intensive operations, i.e., synchronization,
Start-of-Frame-Delimiter (SFD) detecting, and payload decoding are hardwired in
the ASIC block. The ASIP contains firmware for a lightweight MAC and control
algorithms. The combination of ASIP and ASIC allow a flexible but power efficient
design. Moreover, wide parallel processing can be implemented to minimize the
acquisition time and, consequently, enables a more aggressive duty-cycling of the
RF front-end.
During synchronization phase, the frontend is enabled 100 % of the time over
a period of multiple preamble symbols. In this time, the incoming samples are
correlated against a known sequence, whereby a full-, partial-, or non-coherent
correlation can be selected. The pulse position and code phase search are combined
in order to reduce the time in the synchronization phase and support full- and partial-
coherent synchronization. Once the code phase of the preamble symbols is known, the
frontend is duty-cycle between the isolated pulses and the receiver baseband switches
into a preamble tracking/SFD detection mode. A hardware implemented correlator
is used to search for the SFD. After the SFD has been detected, the frontend is
duty-cycled between the burst positions and a hardware supported payload decoding
module is used to decode the payload data.
A frequency tracking loop is implemented to compensate the 50 ppm frequency
offset between the transmitter and the receiver carriers (Fig. 20 ). This is essential
since the fully-coherent reception outperforms partial/non-coherent receivers when
the offset is < 30 ppm. As length of the data symbols is predefined, the frequency
offset is measured from the average phase difference between received symbols.
The measured frequency offset is low-pass filtered and fed back to control the phase
rotator. As such, an offset frequency, equivalent to the measured amount as in Fig. 20 ,
is applied to the received data for compensation. The tracking loop can compensate
up to 63 ppm frequency offset and thus ensure the coherent reception with the free-
running DCO scheme.
Fast Startup Circuit Techniques
The main power reduction technique for the IR-UWB system is the duty-cycled
operation. To fully maximize this property, the system should be strictly turned on
only during operation. At the transmitter side, duty-cycle of the RF front-end is
achievable during the entire data packet. At the receiver side, duty-cycling is only
applicable after the synchronization. Therefore, the RF front-end needs to be turned
on continuously until the digital baseband detects the position of the isolated pulses