UWB for Around-the-Body Data Streaming - Ultra-Wideband and 60 GHz Communications for Biomedical Applications - page 56

When continuously on, the transmitter front-end (excluding the Digitally-
Controlled-Oscillator (DCO)) draws 40 mA from a 1 V supply, and delivers a
maximum 13 dBm peak output power at the output of the IC, with 50 % power
efficiency at 8 GHz. Note that, despite the use of lossy antennas in this application,
this high output power maximizes the emission close to the FCC limits. For the
wireless link evaluation, it is more important to measure the average output power
emitted by the antenna. The average output power obtained at the antenna is − 13

dBm assuming 0 dB gain antenna.

DCO Design

A local oscillator (LO) signal from 6 to 10 GHz is needed in both transmitter and
receiver, to provide the carrier signal. The generation of a stable LO signal from 6
to 10 GHz is very challenging, mainly because of the large frequency range. The
implementation of the oscillation can be chosen between LC-tank based oscillator
and ring oscillator, and here the latter option is preferred for the following reason.
The ring oscillator avoids the use of large inductance, saving the on-chip area and
avoiding the pulling effect in the transmitter. The large frequency bandwidth requires
large tuning bank. In an LC-tank oscillator, it means the quality factor of the inductor
needs to be largely flattened, which decreases the advantage of using inductors for
better phase noise performance. Therefore, a 3-stage ring oscillator is implemented
to reach high frequencies (upto 10 GHz), to have a very large tuning range and a
settling time of few ns.
The oscillator core consists of three stages of differential inverters in a closed
loop, as in Fig. 12 a, and each differential pair is as shown in Fig. 12 b. The instability
created by the odd numbers of stages produces oscillation whose frequency, in the
first order, is defined by the product of RC time and the number of stages N. In each
differential pair, the input pair M1/M2 are switched on/off alternatively by the input
signal IL_1/IR_1. The current from M7 is thus steered between M1 and M2. The
output amplitude at OL_1/OR_1 is the voltage drop across the R load by the biasing
current. Transistor M5/6 are implemented to enable/disable the oscillator.
The frequency can be tuned by altering the inverter stage load resistance R load
or the load capacitance C load . The choice of the RC values is the trade-off between
several design parameters. To achieve high oscillator frequency, the RC value needs
to be minimized. The swing of the DCO output signal is critical to drive the following
stage, and is determined by the product of the biasing current and the R load value.
To balance between the power consumption and the output swing, the R load needs to
be maximized. To cover the wide tuning range and to achieve the fine tuning step,
three tuning banks are implemented. Coarse tuning is based on a 4-bit resistive bank,
changing the resistive load in the differential pairs. Medium tuning is based on a
3-bit capacitive bank, which loads at the output of each stage. The capacitive bank
is realized by switching on/off the CMIM capacitor.
The fine tuning bank (as in Fig. 13 ) is also realized by tuning C load . However, the
target minimum step of 1 MHz requires very small unit capacitance, down to 0.5