Biomedical Engineering Reference
In-Depth Information
Fig. 10
Data packet format
Digital Baseband
As shown in Fig.
3
, the DBB consists of various digital signal processing blocks to
support the bidirectional data communication. For TX, the raw data goes through a TX
FIFO to separate the data into multiple packets suitable for data packet transmission.
The data packet then go through a (8, 4) Hamming encoder which has three parity
check bits and one overall parity bit following every four information bits. It can
correct 1 bit error and detect 2 bits errors for every codeword. The resulting data
packet is then assembled into a packet frame by adding a 16-bit preamble, an 8-bit
start frame delimiter (SFD), a 16-bit PHY header (PHR), and a 8-bit header checksum
(HCS) in front, the packet format is shown in Fig.
10
. The 16-bit preamble pattern
consists of 16 consecutive transmitted “1”s to facilitate the identification of received
UWB pulse location. The 16-bit PHR sequence defines the size of the data payload.
The HCS provides error detection to ensure that the decoded information from PHR
is valid. The packet can accommodate a maximum data payload of 128 bytes. In
addition, long consecutive 0s of payload are avoided by baseband coding because
continuous tracking of pulse location can only occur for received “1”s.
Receiver timing synchronization is the most critical block in the digital baseband.
It includes a pulse searcher and a pulse tracker. Given a sequence of pilot signals,
pulse searcher would identify the timing location of received UWB pulse within a
specific time interval. However, due to clock drift issue between transmitter and re-
ceiver, this identified timing location will also drift with time and become inaccurate.
To circumvent this problem, pulse tracker module is invoked once pulse searcher suc-
cessfully identifies received UWB pulse timing location. It will continuously track
the location of UWB pulse even in the presence of clock drift. It also recovers the
received data into NRZ format and generates the corresponding data clock. Both
the period and duty cycle of data clock are adjusted continuously in the presence of
clock drift. After synchronization, pulse tracker module also generates enable signal
for transceiver's burst mode operation.
A D flip-flop based pulse searching and detection algorithm [
17
] is developed, in-
stead of the power hungry ADC synchronization approach. As shown in Fig.
11
, UWB
pulse searching module consists of four D-flip-flop detectors, a sampling controller,
ten negative edge-triggered 5-bit registers (NR
0
-NR
9
), ten positive edge-triggered
5-bit registers (PR
0
-PR
9
), and a decision finite state machine (FSM). UWB pulses
are detected using the D-flip-flop detector shown in Fig.
11
. For any given data rate,
the system clock is first set to ten times of the data rate through an internal frequency
divider. Each symbol period is then divided into ten smaller duration windows by
the sampling controller. Therefore, one duration window (T
dur
) is equivalent to one
system clock interval (T
clk
). Each duration window within the symbol period is then
tracked by either positive counter or negative counter. In addition, each duration
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