Biomedical Engineering Reference
In-Depth Information
Fig. 6 A 32-kHz crystal on
wireless sensor network
(WSN) node, TelosB [ 24 ]
Table 1 Comparison of
compact frequency references
Crystal [ 21 ]
MEMS [ 22 ]
CMOS [ 23 ]
Manufacturer
Vectron
International
SiTime
Silicon Labs
Volume 9.6 mm 3 4.5 mm 3 11.5 mm 3
Accuracy 25 ppm 50 ppm 150 ppm
Power 82.5 mW 72.6 mW 26.4 mW
MEMS microelectromechanical systems, CMOS complementa-
ry metal-oxide semiconductor
mm-Scale Antennas
Among the building blocks in a WSN node, the antenna plays a critical role because
it is traditionally off-chip for better performance, and its size dominates at least one
dimension of the node. Antennas integrated in a CMOS process have a size advantage
over external packaged antennas; however, reducing antenna size at a fixed frequency,
in general, results in reduced performance [ 25 ]. Antennas can be integrated directly
on-chip, but at the mm scale, the operating frequencies need to be at least 10 GHz
for good radiation efficiency [ 9 ]. However, operating at higher frequency has other
disadvantages. First, the path loss in the wireless channel increases [ 25 ]. As a result,
more signal power is lost for a fixed communication distance. Second, RF front end
circuits that operate at these higher frequencies will consume more power. On-chip
antennas seem to be a good candidate to meet the mm 3 volume requirement of future
sensor nodes, but there are several design trade-offs to consider.
CMOS technology is preferable nowadays of ICs because of its low cost, decent
performance, and ease of integration [ 32 ]. Nevertheless, there are several challenges
for on-chip antenna integration. First, the area occupied by the antenna and the space
for isolating the crosstalk between antenna and active circuits should be considered.
Additionally, the lossy silicon P-substrate (
10 cm) in a CMOS process degrades
the antenna performance significantly because energy dissipates in the substrate
instead of radiating into the air. Moreover, the design rules in CMOS technology such
as metal slotting and density requirements also impact the antenna design. Figure 7
shows the cross section of an on-chip CMOS patch antenna [ 32 ]. In this example,
the patch radiator is in top metal, with the patch ground plane in an intermediate
metal layer, and metal layers below the ground plane are used for routing circuits
under the patch (e.g., DSP and memory). This approach suffers from reduced antenna
 
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