Biomedical Engineering Reference
In-Depth Information
immobilization and hybridization as well as layer-by-layer adsorbed polyelectrolyte
multilayers are presented.
7.2 CAPACITANCE-VOLTAGE CHARACTERISTICS OF A
BARE AND FUNCTIONALIZED EIS STRUCTURE
A DNA-FED is obtained by immobilizing well-defi ned sequences of an ssDNA as a
biological recognition layer on top of the fi eld-effect transducer, which should convert
the specifi c recognition process between the two complementary DNA strands into a
measurable signal (in this case, changes in the capacitance of the functionalized EIS
structure). Figure 7.2 depicts the schematic structure and measuring set-up of a func-
tionalized capacitive EIS sensor for the DNA immobilization and hybridization detec-
tion. For operation, a DC (direct current) polarization voltage ( V G ) is applied via the
reference electrode to set the working point of the EIS sensor, and a small AC (alter-
nating current) voltage ( V
10-50 mV) is applied to the system in order to measure
the capacitance of the sensor.
The complete AC equivalent circuit of a bare EIS hetero-system is complex and
combines components, like the bulk resistance and space-charge capacitance of the
semiconductor, the capacitance of the gate insulator, the double-layer capacitance at
the electrolyte-insulator interface, the resistance of the bulk-electrolyte solution and
the impedance of the reference electrode, all related to the semiconductor, gate insula-
tor, different interfaces, electrolyte, and reference electrode, respectively (see, e.g., [53,
54]). However, for usual values of insulator thickness (
30-100 nm), ionic strength of
10 4 M) and measurement frequencies (below
the electrolyte solution (
1 kHz), the
equivalent circuit of an EIS structure (see Fig. 7.3a) can be simplifi ed as a series con-
nection of the insulator capacitance, C i ε i / d (
ε i and d are permittivity and thickness
of the insulator, respectively) and the space-charge capacitance of the semiconductor,
C sc (
), which is among other things a function of the voltage applied to the system and
the electrolyte-gate insulator interfacial potential (the electrochemical double-layer
capacitance is assumed to be much greater than C i and C sc (
) and therefore can be
neglected) [54].
Thus, the expression for the total capacitance of the bare EIS structure, C (
), is sim-
ilar to the equation for an MIS capacitance, but with a modulation possibility of the
space-charge capacitance by means of the electrolyte solution-insulator interface poten-
tial (
) are usually defi ned per cm 2 surface area):
) (the capacitances C (
), C i , and C sc (
CC
CC ()
()
i c
ϕ
C(
ϕ
)
(1)
ϕ
i
sc
The typical shape of a capacitance-voltage ( C - V ) curve for a p-type EIS structure is
given in Fig. 7.4. As can be seen from Fig. 7.4, dependent on the magnitude and polar-
ity of the applied gate voltage, V G , three regions in the C - V curve can be distinguished:
accumulation, depletion and inversion (an n-type EIS structure shows an identical
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