Biomedical Engineering Reference
In-Depth Information
through a serial register which clocks its content onto the
output sense node. All the charge must be clocked out of
the serial register before the next time line can be
transferred.
During the reading process, the pixels are continually
illuminated, which can result in a smeared image in the
direction charge flow. Data rates are limited by the am-
plifier bandwidth and also by the capabilities of the
analog-to-digital converter. A large array can be divided
into subarrays that are read out simultaneously, the ef-
fective clock rate increases by the number of subarrays.
Figure 6.2-6
illustrates a large array subdivided into four
subarrays. Software can reconstruct the original image,
where the serial data are devoted and reformatted by
a video processor.
A frame transfer image contains two almost identical
arrays. One array is used for image pixel and the other
one for storage. The storage cells are identical to the
light-sensitive cells but are covered with a metal light
shield to prevent any light exposure. Once the in-
tegration cycle is complete the charge is transferred
quickly from the light-sensitive pixels to the storage cells.
The transfer time is around 500
m
s. The smear is limited
only to the time it takes to transfer the image to the
storage area.
V
gate
Metal
Oxide Layer
Depletion
Region
P-Type Si
Figure 6.2-1 The depletion region in semiconductor devices.
CCD arrays. The process creates a serial data stream that
represents the two-dimensional image.
Although any number of transfer gates per detector
can be used, the number generally varies from two to
four. With a three-phase system the charge is stored
under one or two gates. This is shown in
Figure 6.2-4.
Only 33% of the pixel area is available for well capacity.
With equal potential wells, a minimum number of three
phases are required to clock out charge packets efficiently.
As the voltage is applied, the charge packet moves to
that well. By sequentially varying the gate voltage, the
charge moves off the horizontal shift register and onto
a sense capacitor. The clock signals are identical (only one
master clock is required to drive the array) for all three
phases but offset in time (phase).
6.2.1.2 Interline transfer
The interline transfer array consists of photodiodes sep-
arated by vertical registers that are covered by an opaque
metal shield (see
Fig. 6.2-7
). After integration, the
charge generated by the photodiodes is transferred to the
vertical CCD registers very fast and the smear is then
minimized. The main advantage of the interline transfer
is that the transfer from the active sensors to the shield
storage is quick. The shields act like a venetian blind that
obscures half the information that is available in the
6.2.1.1 CCD arrays
Array architecture is dependent on the application. Full-
frame arrays are used in scientific applications. Interline
transfer devices are used in consumer product. In
Figure
6.2-5
we can illustrate a full-frame (FFT) array. After
integration the image pixels are read out line-by-line
1
2
1
2
(a)
(b)
(c)
V
d
V
d
increasing
potential
Well 1
Well 2
1
2
(d)
(e)
(f)
1
2
1
2
Figure 6.2-2 Movement of electrons in a potential well due to photoelectrons.
