Cryptography Reference
In-Depth Information
The decoding performance obtained in practice is very close to that obtained
with floating decimal points for quantizations on 4 to 6 bits (see the table in
Figure 9.18). The influence of the parameters can be studied by the density
evolution algorithm [9.15, 9.11].
9.2.8 State of the art of published LDPC decoder archi-
tectures
The table in Figure 9.18 groups the main characteristics of LDPC decoder cir-
cuits published in the literature so far. The inputs of the table are as follows:
Circuit: description of the type of circuit used (ASIC or FPGA).
Authors: reference to authors and articles concerning the platform.
Architecture:
- Decoder: indication of the type of decoder (serial, parallel or mixed)
with parameters ( P , α p , α v ) associated with the message propagation
architecture.
- Data path: indication for each node processor (variable and con-
straint) of type of architecture used (direct, trellis or total sum).
- Control: indication for each node processor (variable and constraint)
of type of control used, compact or distributed and, if applicable, of
type of update.
- Position of the interconnection network (between 1 and 4).
Characteristics of the LDPC code: size, rate and regularity of the LDPC
code.
quantization format: number of bits used to represent the data in the
decoder.
Clock frequency of the chip in MHz.
Data rate (in bits per second). The information binary rate is obtained
by multiplying by the coding rate.
Maximum number of iterations.
So far, no architecture has been published that describes in detail a decoder
using a sub-optimal algorithm. However, we can mention that of Jones et al.
[9.32], but which contains too little information to be classified here.
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