Cryptography Reference
In-Depth Information
•
This information is then sent to the PNPs via the permutation network,
whose address was generated from the cycle number (read into a memory
for example): this is time permutation.
•
Combining the two describes the random interleaving between the vari-
ables and the first two parities of the bipartite graph shown on the right-
hand part of the figure.
In a single cycle, the first two parities will therefore be able to be processed.
The following two will be processed at the second cycle and so on and so forth,
until all the parities of the code have been processed. Note that this technique
where the PNP information arrives simultaneously prevents two bits contained
in the same VNP being involved in the same parity. Thus, for example, bits
1 and 2 cannot be involved in the same parity otherwise that would lead to a
memory conflict. This solution therefore imposes constraints on matrix
H
,ifwe
want it to be decodable by this structure. One solution to relax the constraints
involves, for example, entering the data serially into the parities.
9.2.4 Combining parameters of the architecture
A certain number of parameters characterizing LDPC decoder architectures have
been defined above:
•
Node processors:
- 3 possible architectures (direct, trellis, total sum)
- 4 possible positions of the interconnection network (see Figure 9.12)
- 3 input-output control modes (compact, distributed with delayed or
immediate update)
•
Message propagation architecture:
- 3 parameters characterizing the level of parallelism
(P,
α
,
β
)
All the combinations of these different parameters are possible to describe or
create an LDPC decoder architecture. Of course, some of these combinations are
more or less of interest, depending on the specifications required. For example,
the combinations of the control modes between VNPs and PNPs, showing the
different possible decoding schedules, are given in Table 9.3.
In the case where the controls on the two processors are of the compact
flow of inputs-outputs type, the schedule performed is of the flooding type:
all the PNPs are processed then all the VNPs. This schedule can easily be
used with completely parallel (
P
=
m
) architectures. For mixed (
P<m
)
architectures, the parities cannot all be processed completely before processing
the variables. The control of the VNPs in distributed mode with delayed update
allows the processing to be done since it guarantees that the new outputs will
