Cryptography Reference
In-Depth Information
avoided after the first iteration if the estimates of the metrics at the boundary
indices are put into memory to be used as departure points for the calculations
of the following iteration.
Figure 7.15 - Operation of the forward and backward recursions when implementing
the MAP algorithm with a sliding window.
The second practical problem is that of the speed and latency of decoding.
The extent of the problem depends of course on the application and on the ra-
tio between the decoding circuit clock and the data rate. If the latter is very
high, the operations can be performed by a single machine, in the sequential
order presented above. In specialized processors of the DSP (
digital signal pro-
cessor
) type, cabled co-processors may be available to accelerate the decoding.
In dedicated circuits of the ASIC (
application-specific integrated circuit
)type,
acceleration of the decoding is obtained by using parallelism, that is, multiplying
the number of arithmetical operators, if possible without increasing the capacity
of the memories required to the same extent. Then, problems of access to these
memories are generally posed.
Note first that only knowledge of permutation
i
=Π(
j
)
is necessary for
implementation of the iterative decoding and not that of inverse permutation
Π
−
1
, as could be wrongly assumed from the schematic diagrams of Figures 7.12
and 7.13. Consider, for example, two SISO decoders working in parallel to
decode the two elementary codes of the turbo code and based on two dual-
port memories for the extrinsic information (Figure 7.16). The DEC1 decoder
associated with the first code produces and receives the extrinsic information in
the natural order
i
. The DEC2 decoder associated with the second code works
according to index
j
but writes and recovers its data at addresses
i
=Π(
j
)
.
Knowledge of
Π
−
1
, which could pose a problem depending on the permutation
model selected, is therefore not required.
