Cryptography Reference
In-Depth Information
Figure 7.12 - 8-state turbo encoder and schematic structure of the corresponding
turbo decoder. The two elementary decoders exchange probabilistic information, called
extrinsic information
(
z
)
.
by
DEC
1
and putting extrinsic information
z
1
in the memory, second decoding
by
DEC
2
and putting extrinsic information
z
2
in the memory (end of the first
iteration), again using
DEC
1
and putting
z
1
in the memory, etc. Different
hardware architectures, with more or less great degrees of parallelism, can be
envisaged to accelerate the iterative decoding.
If we wanted to decode the turbo code using a single decoder, which would
take into account all the possible states of the encoder, for each element of the
message decoded, we would obtain one and only one probability of having a
binary value equal to 0 or to 1. As for the composite structure of Figure 7.12,
it uses two decoders working jointly. By analogy with the result that the single
decoder would provide, they therefore need to
converge towards the same deci-
sions, with the same probabilities
, for each of the data considered. That is the
fundamental principle of "turbo" processing, which justifies the structure of the
decoder, as the following reasoning shows.
The role of a SISO decoder (see Section 7.4.2), is to process the LLRs at its
input to try to make them more reliable, thanks to local redundancy (that is,
y
1
for DEC1,
y
2
for DEC2). The LLR produced by a decoder of binary codes,
relative to data
d
, can be written simply as
LLR
output
(
d
)=
LLR
input
(
d
)+
z
(
d
)
(7.21)
where
z
(
d
)
is the extrinsic information specific to
d
. The LLR is improved when
z
is negative and
d
is a 0, or when
z
is positive and
d
is a 1.
