Cryptography Reference
In-Depth Information
tions systems use independent frame transmissions. Paragraph 5.4.2 showed the
importance of knowing the initial and final states of the encoder during the de-
coding of a frame. In order to know these states, the technique used is usually
called trellis termination. This generally involves forcing the initial and final
states to values known by the decoder (in general zero).
5.5.1 Trellis termination
Classical trellis termination
As the encoder is constructed around a register, it is easy to initialize it by using
reset inputs before beginning the encoding of a frame. This operation has no
consequence on the coding rate. But termination at the end of a frame is not
so simple.
When the k bits of the frame have been coded, the register of the encoder is
in any of the 2 ν possible states. The aim of termination is to lead the encoder
towards state zero by following one of the paths in the trellis so that the decoding
algorithm can use this knowledge of the final state. In the case of non-recursive
codes, the final state is forced to zero by injecting ν zero bits at the end of the
frame. It is as if the coded frame were of length k + ν with d k +1 = d k +2 = ... =
d k + ν =0 . The encoding rate is slightly decreased by the transmission of the
termination bits . However, taking into account the size of the frames generally
transmitted, this degradation in rate is very often negligible. In the case of
recursive codes, it is also possible to inject a zero at the input of the register.
Figure 5.23 shows a simple way to solve this question.
d i
d i r i
,
r i
Mux
s (1)
d i
(3)
s i
D
D
D
1
2
s (0)
(2)
s i
Figure 5.23 - Example of an encoder of recursive systematic convolutional codes al-
lowing termination at state
0
in ν instants.
After initializing the register to zero, switch I is kept in position 1 and data
d 1 to d k are coded. At the end of this encoding operation, instants k to k + ν ,
switch I is placed in position 2 and d i takes the value coming from the feedback
of the register, that is, a value that forces one register input to zero. Indeed, S (0)
i
is the result of a modulo-2 sum of two identical members. As for the encoder,
it continues to produce the associated redundancies r i .
 
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