Graphics Reference
In-Depth Information
Fig. 11.19
Basic one-bin
CABAC pipeline scheme
ctx Input data bins
bypass
state,
MPS
State
is L
P
S?
state is LPS?
range
Range
shift
MPS range
Low
low
output low
Output
BO
output bits
Typical arithmetic coder can be further partitioned into four main stages:
State
,
Range
,
Low
and
Output
.
State
stage will update MPS and state as shown in
Fig.
11.19
.
Range
and
Low
stage will update the range and low values for arithmetic
encoding.
Output
stage will be in charge of outputting the bitstream. Normalization
is performed on range and low after encoding each bin so that they can be
represented with a fixed 9-bit precision. We can see data dependencies between the
four blocks. With this architecture, one bin per cycle is achieved. To achieve better
throughput, pre-normalization circuit may be used to reduce normalization critical
path [
44
]. In HEVC, more than 20 % of the bins are bypass bins. Since the range
update circuit and the context model are not affected in bypass coding, a bypass bin
spitting (BPBS) scheme can be applied to split the process from the bin stream and
remerge into the bitstream before the low update stage [
44
].
For high resolution applications, the throughput of one-bin CABAC is not
enough. Because of CABAC data dependencies, it is difficult to add more pipeline
stages in CABAC. As a result, techniques to encode more than one bin in a cycle
may be needed. Prior related work includes two-bin [
3
,
19
,
20
,
34
] and multi-bin
[
12
,
44
] arithmetic encoder. One method of multi-bin CABAC is cascading. By
cascading the State, Range, Low, and Output circuits and by using a state forwarding
circuit in State stage, a CABAC engine with multi-bin per cycle is achieved as shown
in Fig.
11.20
a, b. Another method for multi-bin CABAC is the state dual-transition
(SDT) approach [
44
]. It combines two state transition tables into one at the cost of
a bigger table. Then, each stage may process two bins per cycle. SDT can also be
combined with cascading techniques.
