Graphics Reference
In-Depth Information
Fig. 11.11
Scalability for
reference memory hierarchy.
TheSRAMsizeisthesumof
all the L3, L2, and L1
reference SRAM size in the
memory hierarchy. The ports
are the supported concurrent
read ports that can provide
data to the processing
engines. More read ports are
supported by increasing the
number of L1 SRAMs
7.4
7.3
7.2
7.1
7
6.9
6.8
6.7
6
8
10
12
14
16
18
Supported Read Ports
Fig. 11.12
Analysis of the
strategy for search window
data reuse
SRAM Size per Ref. Frame (KB)
For the top L3 level memory, we did an analysis on the strategy for level C,
level C
C
, and level D. The analysis result is shown in Fig.
11.12
. Note that the level
C
C
strategy uses a non-raster scan CU order and requires frame-level pipeline at
entropy stage. As can be seen in Fig.
11.12
, the bandwidth of level C
C
strategy
is bigger initially, and drops down quickly below that of Level C strategy as the
SRAM size increases. That is because frame-level pipelining is a must for level
C
C
strategy, so frame-level I/O overhead dominates at the beginning. However, the
bandwidth gain for level C
C
strategy quickly overrides the penalty from frame-level
entropy pipelining. Depending on the requirement, level C
C
or level D strategy is
more suitable for L3 level memory.
The detailed data flow is shown in Fig.
11.13
. IME requires the data in subsam-
pled pattern, while FME requires data in fully sampled pattern. To support the two
kinds of data pattern, we have two kinds of data ordering in SRAM. One is able to
support subsampled pattern. The other is able to support fully sampled pattern.
Data exchange among stages is done with round-robin style memory multiplex-
ing. Since the Ref. L2 SRAMs and the Ref. L1 SRAMs are of the same size, we put
one set of L1 SRAM and L2 SRAMs in the multiplexing to save SRAM usage.
