Graphics Reference
In-Depth Information
Chapter 11
Encoder Hardware Architecture for HEVC
Sung-Fang Tsai, Cheng-Han Tsai, and Liang-Gee Chen
Abstract
In this chapter, an encoder hardware architecture design for HEVC is
described. The system pipeline is first introduced followed by the design details
of the different HEVC encoder modules such as inter prediction, intra prediction,
mode decision, in-loop filters, and entropy coding. Finally, a sample test chip
implementation result is presented as a reference.
11.1
Introduction
High density large-sized displays that provide an immersive display experience
are being widely adopted in multimedia application terminals. The next genera-
tion display panels are expected to be 4K/8K (Ultra High Definition Television
(UHDTV) resolution) or even higher. As a result, the video resolution required is
also becoming higher. To reduce the storage and transmission requirements of large-
sized video, HEVC video encoding, that provides around 50 % better compression
efficiency than H.264/AVC, is recommended. However, real-time high resolution
video encoding in HEVC requires hardware support due to the complexity.
The HEVC Test Model (HM) is the reference software for HEVC developed
during standardization of HEVC. The HM encoder was designed to maximize the
coding gain achievable by HEVC. Real-time performance was not a major objective.
The HM encoder can be used for a wide variety of applications including offline
encoding [
30
]. However, the encoding methods in HM do not necessarily map to the
most efficient design for a real-time hardware encoder. Hardware consideration is
quite different from software and is very challenging. For H.264/AVC, many state-
of-the-art H.264/AVC encoder architectures [
4
,
5
,
18
,
23
,
43
] have been presented.
S.-F. Tsai (
) C.-H. Tsai L.-G. Chen
Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
