Graphics Reference
In-Depth Information
pipeline to process the wide range of Coding Tree Unit sizes and account for
variable DRAM latency. The challenge of large and varied sizes of Transform
Units can be addressed using Multiple Constant Multiplication and an SRAM-
based transpose memory for an area-efficient implementation. Similarly, the use
of Time-Multiplexed Multiple Constant Multiplication to optimize HEVC's longer
interpolation filter was described. The longer interpolation filter also results in
increased bandwidth requirement from reference picture buffer which is addressed
by a cache and a DRAM-latency aware memory mapping. The design of a
hierarchical memory organization was described to handle the pixel flow for intra-
prediction and the main considerations for designing HEVC's in-loop filters were
enumerated. Finally, simulated and measured power results for the test chip were
shown.
Acknowledgements
The authors gratefully acknowledge the support of Texas Instruments for
sponsoring the HEVC decoder test chip project and Taiwan Semiconductor Manufacturing
Company (TSMC) University Shuttle program for manufacturing the chip.
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