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In-Depth Information
needed. These buffers store pre-SAO pixels and their SAO parameters. However,
unlike intra prediction, the choice of pipeline granularity is very flexible and can be
chosen based on throughput requirements. Unlike deblocking filter which operates
on a edge basis, SAO operates on a per-pixel basis. So, the two in-loop filters have
a comparable computational complexity even though SAO computation involves
mainly comparison and addition.
Zhu et al. [
30
] describes an architecture for SAO that is capable of 8K Ultra-HD
(7;680
4;320) at 120 fps. In spite of such high throughput requirement, the design
takes only 36.7 kgates in 65 nm technology.
10.9
Implementation Results for Decoder Test Chip
A decoder test chip was implemented in [
9
] with a core size of 1:77 mm
2
in 40 nm
CMOS, comprising 715K logic gates and 124 kB of on-chip SRAM. Figure
10.22
shows the micrograph of the test chip. It is compliant to HEVC Test Model
(HM) 4.0, and the supported decoding tools in HEVC Working Draft (WD) 4
are listed in Table
10.14
along with the main specs. The main differences from
the final version of HEVC are that SAO is absent and Context-Adaptive Variable
Fig. 10.22
Chip micrograph
