Graphics Reference
In-Depth Information
7x4 MAUs Fetched
23 x23 Reference Region
Minimum Access Unit
(MAU) of 8x4 pixels
16x16 Predicted
0
1
2
3
0
1
Cache Datapath Index
Fig. 10.16
16 PU. Seven
cycles are required to fetch the 28 MAU at 4 MAU per cycle. Note that the dispatch region and
the four parallel cache datapaths may be misaligned, thus requiring a reordering. For example, the
region in this figure starts from datapath #1
Example of MC cache dispatch for a 23
23 reference region of a 16
Table 10.10
Comparison of twisted 2D mapping and direct 2D mapping
LD
RA
Encoding Mode
CTU Size
64
32
16
64
32
16
ACT BW
Direct 2D
272
227
232
690
679
648
(MBytes/s)
Twisted 2D
219
183
204
667
659
636
in
0% 0% 2%3%3%2%
Minimizing Row Precharge and Activation.
The Twisted 2D mapping of
Fig.
10.14
ensures that pixels in different DRAM rows in the same bank are at least
64 pixels away in both vertical and horizontal directions. It is unlikely that inter-
prediction of two adjacent pixels will refer to two entries so far apart. Additionally
a single dispatch request issued by the MC engine can at most cover four banks. It
is possible to keep the corresponding rows in the four banks open and then fetch
the required data. These two factors help minimize the number of row changes.
Experiments show that twisting leads to a 20 % saving in bandwidth over a direct
mapping as seen in Table
10.10
.
Minimizing Conflict Misses.
A conflict miss occurs when two locations in mem-
ory map to the same cache line. To mitigate this, we need to select an appropriate
mapping between the DRAM addresses and the cache line indices. Setting the line
index to the 7 bit column address of the MAU ensures that two conflicting pixel
location in the same picture are at least 64 pixels apart. However, the same pixel
location across two pictures will map to the same cache line. Similarly a luma and
an unrelated chroma address may also map to the same cache line. Using 4-way set
associativity in the cache helps resolve both these conflicts.
