Graphics Reference
In-Depth Information
Table 10.8 Gate count of
inter architecture when
synthesized at 200 MHz in
40 nm CMOS. SRAM sizes
are also summarized
Logic area
(kgates)
Module
SRAM (kbit)
Dispatch
4.7
2.2 (two-port)
Fetch
12.0
28.8 (one-port)
2-D Filter
50.0
n/a
Inter Ctrl
2.7
n/a
To t a l
69.4
31.0
Table 10.9 Gate count
breakdown for the 2-D filter
Logic area
(kgates)
Sub-module
Input Mux
4.8
H Filter
12.0
V Filter
21.8
Register Chain
9.4
Bi-Sum
1.2
Ctrl
0.8
To t a l
50.0
Since most of the gates are for the 2-D filter, its gate count is given in more detail
in Table 10.9 . For the 2-D filter, the horizontal and vertical filters occupy the most,
and the area of horizontal ones is nearly one half of that of vertical ones due to their
smaller internal bitwidth. This implementation does not include all PU Types used
in the HEVC standard (Asymmetric Motion Partitions 32 8, 8 32, 16 4, 4 16
are not implemented), and so, uses only eight horizontal and eight vertical filters.
10.6
MC Cache and DRAM Mapping
HEVC's longer interpolation filters cause a significant increase in the required
motion compensation (MC) bandwidth to the reference picture buffer (a.k.a.
decoded picture buffer—DPB) as compared to H.264/AVC. However, there is
significant overlap in the reference pixel data required by neighboring inter PUs
which can be exploited by a cache. Most video codecs use DRAM based memory to
store the DPB since it can be several megabytes large. In such a scenario, in addition
to reducing the bandwidth requirement, the cache also hides the variable latency of
the DRAM. This section describes the design of a read-only MC cache to support
real-time decoding of 4K Ultra-HD HEVC video.
The target DRAM system is intended to store six reference pictures at 4K Ultra-
HD resolution (corresponding to HEVC level 5) in addition to the collocated motion
vector data. The DRAM system is composed of two 64M 16-bit DDR3 DRAM
modules with a 32 byte minimum access unit (MAU). A single MAU is mapped to
a cache line.
 
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