Graphics Reference
In-Depth Information
Table 10.7
Gate counts of the described and reference designs for the x 3 , x 4 ,andx 2 j
x 5
TMMCM in the vertical filter based on 40 nm process synthesis results
Design
x 5
Timing 1 ns 2 ns 1 ns 2 ns 1 ns 2 ns
Reference (gates) 1144 547 557 526 2284 845
Proposed (gate) 1036 518 442 361 1578 738
Area reduction 9.4 % 5.4 % 20.6 % 31.4 % 30.9 % 12.6 %
The reference designs for x 3 and x 4 are generated by [ 15 ], and the reference for x 2 jx 5 is
designing x 2 and x 5 separately
x 3 TMMCM
x 4 TMMCM
x 2 j
TMMCM
TMMCM
Fig. 10.13
HEVC interpolation filter design using 13 adders
unsigned and signed inputs, and the outputs can be magnified at most by 88 and
112 times respectively. So, the 1-D horizontal filter has 8-bit unsigned input and
16-bit signed output, and the vertical one has 16-bit signed input and 23-bit signed
output.
10.5.4
Implementation Results
For supporting 4K Ultra-HD 30 fps videos, this architecture is synthesized at
200 MHz in 40 nm CMOS. The result is shown in Table 10.8 . The total gate count is
69.4k, of which 50.0k for the 2-D filter. The Fetch module mainly consists of large
multiplexers and results in 12.0 kgate. The Dispatch module occupies 4.7 kgate for
the block size and position calculation. The total SRAM size is 31 kbit, including
the two-port 2.2 kbit Dispatch Info SRAM and the single-port 28.8 kbit Reference
Data SRAM.
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